• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 63 subscribers
  • Views 95 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS7H1111-SEP: Ramp up of the output of the TPS7H1111MPWPTSEP

Elisa Rodriguez de la Rosa
Prodigy 30 points
Part Number: TPS7H1111-SEP
Other Parts Discussed in Thread: TPS7H4010-SEP

Tool/software:

HI,

I want to generate a voltage of 3.75V using the LDO TPS7H1111MPWPTSEP. For that purpose, I implemented the following circuit. 
The 5V input are coming from a DC/DC the TPS7H4010-SEP whose switching frequeny is set to 350kHz. 

To set the output voltage to the desired level, I connected a Rref=12k to the REF pin and Rset= 37,4k to the SS_REF pin. The Css added in parallel with RSET allows a better stability and a lower output noise and set the soft start time to 7.8ms.

The CLM (current limit mode) is connected to Vin for brick-wall current limit mode.

Rfbpg_top= 100k and Rfbpg_bot = 10k so that the theoretical threshold output is set to 3.366V.

A capacitor (CCOMP) and resistor (RCOMP) of 4.7 nF and 5 kΩ recommended are placed in series to the STAB pin to compensate the device.


The Css at the soft-start pin as been replaced by two 10uF in parallel to set the soft start time to ~34ms.

The VSK is enabled by the output of a Latching circuit (powered with the 5V), which during start up is inhibited to that its output follow the ramp up of the 5V.

At start up we observed the following behavior (the 3V75 trace is not relevant here, we are interrested in VSK):

 

VSK which is the output of the LDO ramps up to 3.25V in ~34ms than only reach slowly 3.75V is ~2.5s.


Do you have any idea why VSK would not ramp up directely to 3.75V in ~35ms?

Thank you in advance for you help

  • +1
    TI__Genius 12150 points

    Hi Elisa,

    This behavior is due to the selected FB_PG resistors and CSS caps. As you mentioned, the resistors in your schematic set the nominal VOUT_assert threshold to 3.366V. There is some part-to-part variation of the FB_PG threshold (306mV typical) and the external resistors will also have some tolerance, so the actual VOUT_assert threshold that you observed was ~3.25V. 

    When enable goes high and soft start begins, the CSS capacitors are initially charged with ~2.1mA. This 2.1mA is the combined current from I_SET (100uA) + I_FAST_START (~2mA). Once VOUT reaches the VOUT_ASSERT threshold set by the FB_PG resistors, the soft start time ends (~34ms) and the 2mA I_FAST_START is removed. This means that only I_SET (100uA) remains to charge VOUT to the final value of 3.74V, so the resulting RC charging time can be fairly long depending on the selected CSS. Figure 8-3 and Figure 8-4 in the datasheet describe this behavior.

    Thanks,

    Sarah