LM5123-Q1: Request for layout design review

Hello Jeffrey,

Here are my comments on the layout:

Please connect the PGND polygon on the TOP layer directly to the PGND pin with a wide connection (next to LO pin)
Maybe move that VIA next to the VCC capacitor out of the way to make some space.

LO and the connection between the source of the Low-side FET and the PGND pin (pin10) should be routed like a differential pair.
Also, HO and SW should be routed like a differential pair.
Next to each other or on adjacent layers directly on top of each other.

Move C13 and C14 close to the source of the high side FET.
The same is true for the bigger ceramic capacitors.

Use many more VIAs to connect the GND polygons on the top layer to the PGND plane (Signal 2 layer) close to the solder pads of the components (especially FETs and capacitors).

Just as a repetition, in my previous post in the old thread, I wrote:

> ... do not use any thermal-relief connection for any component of the power stage nor for the capacitors on the VCC pin.

A proper connection of the ceramic input and output capacitors is mandatory.
Parasitic resistances and inductances of the thermal relief connections will cause big issues.

Please do not route the current sense lines underneath the FETs.
Even if the length will increase, please route these differential tracks from the sense resistor around the electrolytic capacitors to the controller.

All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults” and is subject to TI’s Important Notice: www.ti.com/.../important-notice.shtml

Best regards
Harry