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UCC21710: Gate driver tripping on over current fault when it is already bypassed.

Part Number: UCC21710
Other Parts Discussed in Thread: UCC5390

Tool/software:

I am using UCC21710 as a part of Wolf-Speed Evaluation Board. However the gate driver trips spuriously on over current fault. The protection is bypassed by connecting the source to the appropriate JT connector.

Furthermore, I have shorted pin 2 (OC) and pin 3 (COM) so there should not be any FLT(active low) signal. However ,still the driver spuriously trips.

Any other ways to bypass the trip.

Another Question: In my case the EN signal is always high. Is this the right way to reset the fault?

Note: This is part of an ANPC Inverter circuit. The driver trips when the DC Link Voltage crosses a certain threshold.

  • Hi Ankit,

    This behavior is related to the way the output die communicates faults with the input die. There is an on-off keying circuit on the input side that that counts for 3 rising edges from the fault detection circuit on the output die. However, an OUT falling edge can cause a cross-channel noise similar enough to incorrectly triggers nFLT. One way to limit this problem is to slow the OUT falling edge to eliminate undershoot. The problem is worst at cold temperature, which reduces the effectiveness of internal filters.

    Yes, you can re-set the nFLT by sending a  negative pulse on the EN/nRST pin.

    If you want greater simplicity, you can use a gate driver such as UCC5390 that does not have this nFLT as a potential failure mechanism.

    Best regards,

    Sean

  • Hiiii Sean,

                    Thank you very much for your suggestions. The fundamental problem seems to be the "OUT" falling edge causing a cross channel noise.

    Is there any other means external to the gate driver, that I can use to reduce the impact of this channel noise. Would an external shield help in such a case?

    Any reason, why this problem exacerbates when the external DC Voltage on power side is >450V?

    I do not need this protection at all, so any means required to bypass it would be acceptable.

    Regards,

    Ankit

  • Hi Ankit,

    My colleague has tested a high-voltage ~100pF capacitor across the isolation barrier to shunt this noise with some success. This can work on the low-side, since there will not be any charge cycling. 

    Higher HV Bus voltage usually means higher noise during switching.

    Best regards,

    Sean

  • Hiii Sean,

                    Thanks for helping me with this. Across which two pins on the gate driver should I add this capacitor? 

    Regards,

    Ankit

  • Hi Ankit,

    She added this capacitor across the grounds. Hopefully you have a gound plane on the input side that can absorb the noise injection without creating a ground-bound issue.

    Best regards,

    Sean

  • Hiii Sean,

                   Is it a good idea to add this capacitor on high side gate driver as well?

    Regards,

    Ankit

  • Hi Ankit,

    Adding a capacitor between the high-side ground (Switch node) and the logic ground is NOT an good idea. The capacitor will heavily load the switch node, and add lots of losses to the FETs, In addition, it will inject high AC current into the logic ground.

    It is not really a good idea to add a capacitor across the low-side gate driver either, but it was found to mitigate the UCC21710 false triggering of nFLT in my colleague's testing.

    Best regards,

    Sean

  • Hiii Sean,

                     Thanks for the recommendation. I will try the things suggested by you and get back to you.

    Regards,

    Ankit