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TPS62740: Chip enable when the supercap is fully charged

Part Number: TPS62740

Tool/software:

Hello,

I would like to know if it is possible to activate the enable signal when the supercap connected to the TPS62740 is already charged. What behavior should I expect?

I am currently experiencing a malfunction of the TPS62740, and I wanted to know if it could be due to this activation. Perhaps it is not allowed?

Thank you in advance for your support.

  • Hi Andrea,

    Thanks for using E2E.

    Please take a look to the data sheet topic 9.4.1 which should help you to get the system running correctly.

    Best regards,
    Sepp

  • It really seems that residual charge voltages on the supercapacitor could affect the proper startup of the main system and the subsystem.

    Where can I find additional details to better understand this issue?
    Why could a voltage on the supercapacitor impact proper startup?
    What could happen if I do not comply with this condition?

  • Hi Andrea,

    I will try to get more information about this behavior and will come back to you asap.

    Best regards,
    Sepp

  • Thank you, Josef.
    In my application, sometimes I see a continuous voltage of 3.45V on Vout.
    However, the maximum my firmware set with the VSEL pins is 3.2V.
    This should not be possible with the TPS62740.

    One thing I do is set the EN pin to 0 and then back to 1, perhaps too quickly for the supercap connected to Vout to discharge.
    I was wondering if this startup condition could lead to the incorrect regulation of 3.45V.

  • Hi Andrea,

    Please see the application note which explains how to use the TPS62740 with a supercap.

    Efficient Super-Capacitor Charging with TPS62740

    Do you following this setup? What is the behavior of the malfunction?

    Best regards,
    Sepp

  • Yes, I followed this guide and created this design.
    The supercap is SCMT22F505PRBA0 with a 5F capacity.
    In my test, V_PRIMARY is 3.6V, supplied by a bench power supply.
    The VSEL pins are set to regulate 3.2V.

    At some point, I measured a DC voltage of 3.45V on V_SUPER_CAP.

    In my application, the EN pin is frequently toggled.
    My suspicion, though I don't rule out other possible reasons, is the following:
    Starting from a correctly regulated 3.2V on VOUT, the EN pin goes to 0 and then back to 1 without allowing VOUT enough time to reach 0.
    I fear that the buck converter enters a malfunctioning state if it tries to set a voltage lower than what is already present on VOUT, given that a charged supercap is connected to VOUT.

    I would like to understand whether my suspicion is correct (and if my suspicion is correct, to be able to justify it with a theoretical basis) or if there is an error in my design that could lead to more than 3.2V on VOUT.

  • Hi Andrea,

    We are not able to detect an issue on the schematic which could lead to the malfunction.

    Could you please provide 2 scope plots (good and bad behavior) to show the VOUT, V_SUPER_CAP and EN voltage when you are switching off and on the EN pin.

    Best regards,
    Sepp