Other Parts Discussed in Thread: TPS40170, LM5145
Tool/software:
We are implementing an OVP/UVP circuit on the output of this part and pulling the Hside FET gate low during a fault condition. Is there any harm with loading HDRV (pin17) with a weak pulldown?
The datasheet says min voltage of HDRV is Vsw which is -5V, so I think I am good there. Is there any other issue with this connection (Current output, SW pin, faults)? The sim doesn’t seem to allude to any issues.
Also, I do not see a datasheet time value for Enable/Disable (pin1) to nominal Hside/Lside FET operation, are there any numbers on this? We are considering using this as a backup if disabling the Hside FET option doesn’t work out.