TPS65219: PMIC having a strange behaviour of buck3 during power-up

Hi Jorgen,

Looks like there is a leakage path from rails powering Buck2 and Buck3.

Is DVDD3V3 applied to the processor before Buck2?

Sathish

Hi Satish

Just measured this morning and yes the DVVD3V3 that is enabled by the GPO2 from the PMIC is on during the initial state since the GPO2 pin is disabling the DVVD3V3 first after this first try/failed start-up. The time before the GPO2 is set low is close to 100ms after the first try/power is applied. This way to me it seems unavoidable to have this first residual voltage error. This plot shows the GPO2 signal (yellow line). The blue, red  and green as above

Hi Jorgen,

We need to find out the leakage path between Buck2 and Buck3 rails. Is it possible to measure the impedance between the two when the board is not powered?

Sathish

Hi Satish

Since we are using the AM625SIP with the DDR-Ram on-top of the CPU there is no other connection externally between the buck2 (DVVD_1V8) and the buck3 (VDDS_:DDR (1.1V)). The problem is that the GPO at start is not held at "0" thus enabling the external DVVD3V3. The GPO is OK first after approx. 100ms which you se on the scope-plot. This situation is the same also if the PMIC has power applied all the time and is forced ON by a short button press. I think that we can mitigate the problem by resetting the involved registers in the PMIC shortly into the UBOOT but this behavior is not what I read from the DS of the TPS6521902 which is intended for use with the AM625SIP....

I have measured the impedance to 4MegOhm between B2 and B3 using 200mV as measuring voltage.

Kind regards

Jørgen

Hi Jorgen,

GPIO2 is the first signal to come up after PMIC is powered up and this is used by enternal load switch to provide DVDD3V3.

I am not sure how you want to mitigate the problem by resetting the registers. 

Did you check with AM625 team on the power up requirements or the rail powered by Buck3 pulling up by rail on Buck2?

If there is no AM625, PMIC would not behave like this. For TPS6521902, Buck3 would comes up 3ms after Buck2 powers up.

Sathish

Hi Satish

Yes I understand that the GPO2 comes up regardless of the outcome of the PMIC start-up. It is pulled down later if the start-up fails.

Would a solution OR-gating the GPO2 and DVDD1V8 (buck2) with a delay of 1ms solve the problem with the leakage -> residual voltage detected?

By resetting the PMIC errors registers I can avoid the errors messages later into the boot process.

Kind regards

Jørgen

Hi Jorgen,

I am not sure, but i think you need to understand why Buck3 gets pulled up while Buck2 is powering.

Also, why GPIO2 has the dip on power up?

You mentioned above that GPIO2 is not held at 0 at startup thus enabling external DVDD3V3, but that is the expected behavior. On PMIC power up, GPIO2 is the first signal to come up.

Sathish

Hi Satish

Since we use the PMIC and the AM625SIP with DDR-RAM We have no external connection between these power-domains (except from the PMIC of course). 

I have made a setup that automatically forces the PMIC to shut-down and then ON again shortly after using the button-press. This is all done with power applied constantly to the PMIC and the loadswitch for the DVDD3V3 which is controlled by the GPO2. This is to se whether I get other errors which are normally difficult to catch. I'll return with the results.

Kind regards

Jørgen 

Hi Jorgen,

Sure, let me know the results.

Sathish

Hi Satish

Did the start-up -> shut-down -> start-up thousands of times with the same conditions: having power applied to the PMIC always. The result is always the same: 1.st sequence fails and the next is OK. There is no exception to this. I think that for now this is acceptable and we can clear the register that is set before the Linux boots thus avoiding errors. I still think that it is odd that I see this issue since we use the PMIC version 02 that is intended for use with the CPU we use: AM625SIP. So If other customers have the same issue and may have a solution I certainly would appreciate a note in this thread.

Hi Jorgen,

Sorry about that but glad a workaround exists for you.

I didn't hear any such problem on TPS6521902. Can you check with AM625 team if they can think of something that could happen. 

How are LDO4, LDO1 and LDO3 rails coming up?

If this sequence is okay you can try disabling both Buck2 and Buck3 by I2C after start up and just enable Buck2 and monitor Buck3 voltage.

Sathish