• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 92 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS3808: what the reset pin behavior during VDD<1.7V

dimitry chen
Expert 1145 points
Part Number: TPS3808

Tool/software:

We are using TPS3808G01 for our new project design.

Our architecture is:

  • Our Sense signal, we keep it in safe zone, ya. (First power-up, and > 0.405V)

We have some questions:

  1. VDD < 0.8V, is undefined state, right?
  2. When VDD ramp up from 0.8V to 3.3V, Reset pin, will it driving low, possible?
  3. VDD < 1.65V, then Reset pin, for sure low state, is it?

We need to clarify these points, thanks.

  • 0
    TI__Genius 9870 points

    Hi Dimitry,

    If VDD< 0.8V - > The device has not enough power and therefore the output is unknown. It could be high or low. 

    If  0.8< VDD<1.7V - >  the RESET signal is asserted and low impedance, respectively, regardless of the voltage on the SENSE pin.

     If VDD> 1.7V - >  the RESET signal is determined by the voltage on the SENSE pin and the logic state of MR.

    Hope this clarify! 

    Best,

    Sila