Tool/software:
Hi,
In the UCD90xxx FAQ document it is described that a 1ms interval is required between PMBus inquiries. In the linux kernel driver for this chip I found the following comment:
It has been observed that the UCD90320 randomly fails register access when
doing another access right on the back of a register write. To mitigate this
make sure that there is a minimum delay between a write access and the
following access. The 500us is based on experimental data. At a delay of
350us the issue seems to go away. Add a bit of extra margin to allow for
system to system differences.
We are planning to use this device in a critical application. Can you please elaborate further when exactly this interval is required? According to the comment above there's only an issue when doing another access right after a write. Would this mean that read accesses do not need the interval? Is this applicable to all write commands or only a select set?
Thanks in advance
B.
