• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 63 subscribers
  • Views 194 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC28C43-Q1: Ivdd consumption during soft start of the controller

Chaitanya Koppaka
Prodigy 10 points
Part Number: UCC28C43-Q1
Other Parts Discussed in Thread: UCC28C43

Tool/software:

Hello Team,

I'm using the UCC28C43 as the flyback controller (DCM operation). I have designed a startup circuit to supply the controller intially. This will supply until the flyback output is ready to takeover the controller consumption. At slow ramp up of flyback input voltage, the Startup Circuit (SUC) will supply the energy and increases the Vdd of the controller. When Vdd reaches the ON threshold the controller draws some energy from the Vdd capacitors to generate Vref and after some time the PWM. The PWM duty will gradually increase to its full value when the soft start time is completed. Now my question is related to the energy required by the controller during this soft start phase of the controller. 

In my application, the soft start time is chosen as 180ms (replaced 1uF CSS cap with 10uF for these measurements). When the input voltage of flyback ramp up is faster (80V/s), the energy coming into the Vdd capacitors is sufficient to deliver the controller requirement. Hence the PWM are generated and the flyback can take over the consumption of controller and bypassing the SUC.

But when the flyback input voltage ramp up is slower (10V/s), there are no PWM generated. Beacuse some events are happening in the controller which need energy from the Vdd capacitors and this drops the Vdd below the Turn OFF threshold of the controller and turns OFF the controller. This is kind of a hiccup mode and continous as shown in the below image.

 

Could you please explain the following queries in this context:

1. What happens inside the controller after VREF is generated and before PWM pulses are generated?

2. How much current does the controller need during this phase of operation?

3. Does increasing or decreasing the soft start time will influence the amount of energy required by the controller? If YES how will it influence?

Awaiting your quick answer!! Thanks in advance!!

Chaitanya K

  • 0
    TI__Guru 73595 points

    Hi,

    1.

    IC enables RTCT, then checking CS, FB and COMP to prepare OUT pulses.

    2.

    Up to 3mA based on the datasheet.

    No, change soft start does not change the IC inside circuit biasing need. Soft start time is to affect when the OUT pulses start (COMP > 1V) when switching start when the switching current addition starts.

  • 0 in reply to Hong Huang
    Prodigy 10 points

    Hello Hong Huang,

    Many thanks for your quick answers.

    For topic 3, if the soft start doesn't change the IC consumption. Then could you please help me understand the following behaviour.

    At minimum load (say 1W) on flyback output and 18ms soft start setting, the controller is able to generate PWM. In this case the input current from start up is less so the hiccup mode. When Vdd above ON threshold, the PWM is generated. But the controller energy requirement discharges the Vdd and controller turns OFF when Vdd goes below OFF threshold.

    At very light load (say few tens of mW) on flyback output and 180ms soft start setting, the controller is not able to generate PWM at all. Why is this happening?

    Thanks in advance!!

    Have a nice evening!!

    Chaitanya K

  • 0 in reply to Chaitanya Koppaka
    TI__Guru 73595 points

    Hi,

    Longer soft start time requires more energy from VDD capacitors before switching (i.e. before COMP reaches > 1V). So longer soft start time has longer time to make COMP > 1V, but during this time, still consume energy to make VDD capacitance voltage lower, the current still the same up to 3mA. That is why.

    So for longer soft start time, VDD capacitance needs bigger to store enough energy to keep VDD not off so to allow COMP reaches > 1V and also allows the AUX to take over.  

  • 0 in reply to Hong Huang
    Prodigy 10 points

    Good morning Hong Huang,

    Thanks for your answer. I'm replying again as I need some more clarifications?

    Do you mean that longer soft start time needs same energy (0 to 3A ) for longer duration? How does the Css capacitor charge? From Vref or Vdd? 

    How can I size the Vdd capacitor for longer soft start times?

    Have a good start to the week!!

    Chaitanya 

  • +1 in reply to Chaitanya Koppaka
    TI__Guru 73595 points

    Hi,

    Yes, longer soft start time needs more energy due to the same current about 3mA to bias the IC for longer time. Css capacitor charge through COMP pin current through the bipolar transistor and through VREF through the resistor as show below.

    0.5 x Cvdd [(VDD_on)^2 -(VDD_off)^2] = 3mA x VDD_on x tss

    Solve Cvdd from the above for Cvdd initial value, and bench tune up Cvdd to finalize.

    Cvdd - VDD capacitor value

    VDD_on, VDD UVLO on threshold,

    VDD_off, VDD UVLO off threshold,

    tss, soft start time.