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TPS92682-Q1: TPS92682 SPi waveform problem

zhang lin
Intellectual 310 points
Part Number: TPS92682-Q1

Tool/software:

Hello, expert.

The SPI waveform of TPS92682 is also measured. The waveform of TPS92520 is found to be different. The rising and falling time is relatively long. Our configuration is as follows: 1 TPS92682 +3 tps92520, the MISO pull-up resistor of TPS92682 is 2k, and the TPS92520 pull-up resistor of each piece is 4.7k. We try to remove the pull-up but the effect is worse.

We want to know the reason why the rising edge and falling edge slow down, is it related to PCB?

  • 0
    TI__Expert 5740 points

    Hi Zhang,

    It is likely due to the capacitance from the PCB traces which form an RC time constant. You can either change the pull-up resistor or modify your traces to be similar to one another.

    Here is another post that explains this further: 
    https://e2e.ti.com/support/power-management-group/power-management---internal/f/power-management---internal-forum/1453797/tps92682-q1-spi-waveform-review/5581779?tisearch=e2e-sitesearch&keymatch=SPI%20wave#5581779



    Please let me know if I can further assist you.

    Best,
    Daniel 

  • 0 in reply to Daniel Louis
    Intellectual 310 points

    Thank you for your reply.

    1. I would like to ask more details. How should I adjust my pull-up resistor and how should the minimum value be considered;

    2. I need to add pull-up resistors to the MOSI pins of each chip, or I only need to place pull-up resistors on 1 chip;

    3. Should the pull-up resistor be placed close to the chip or close to MCU;

    4. At this stage, I may not be able to adjust the PCB design, but I would like to know how to improve the PCB in the future, for example, to reduce vias, will it be effective? 

    Sorry, I can't open the URL you sent me.

  • +1 in reply to zhang lin
    TI__Expert 5740 points

    Hi Zhang,

    We can see by the waveforms that the time constant of the SPI bus waveform of TPS92682 is too large and therefore you will need to reduce the resistor value of the pull up resistor at the MISO line (τ=RC).

    MISO is an open drain and therefore you have a pull-up resistor attached to VCC. The time constant is determined by that resistor and the bus capacitance of your PCB layout. Because it's an open drain device, a FET is necessary to pull down that voltage to a logic low, but that FET has its own RDSON which will act as a voltage divider in tandem with the pull-up resistor mentioned earlier. If the pull-up resistor is not sized properly relative to the RDSON of the FET, then the logic level will fall between high and low and will cause an error.

    Find a resistor value that ensures proper communication between your channels and make sure it doesn't cause loading. Resistor values between 5k and 10k are typical. Make sure to size them based on your requirements.

    3. I don't think it matters as long as you "tune" it properly to account for the phenomenon I mentioned above.

    4. In general, we like to see MISO/MOSI lines configured as a differential pair with regard to trace design. This means that they should be the same length and routed right next to each other to minimize noise. Additionally, you should try to avoid routing near the clock as it is likely to couple onto your signal which could cause issues when sending data. Try designing the lines so that they have the same capacitance and please keep the traces as short as possible.

    Here are a few app notes that go more in depth on this subject:

    https://www.ti.com/lit/an/spraar7j/spraar7j.pdf?ts=1743177082731&ref_url=https%253A%252F%252Fwww.google.com%252F
    https://resources.pcb.cadence.com/blog/2019-tips-for-optimal-high-speed-spi-layout-routing

    Best,
    Daniel