UCC28740: Oscillation Stop Behavior of UCC28740

Hi Ning,

Thank you for your reply. I'm not sure if I've conveyed the exact intent of my question, so I'll comment below. I'd appreciate your response.

Ning Tan said:

Q1: leading edge blanking is 230nS nominal. So no CS protection within the first 230nS when the DRV is activated. The delay is negligible.

We understand the LEB (Leading Edge Blanking) function of the CS pin. In the current observed behavior, we suspect that immediately after the LEB period ends, the CS voltage reaches the threshold and is falsely detected, causing the FET to turn off immediately. This results in extremely short ON-time pulses, and we believe that some protection function is subsequently triggered, leading to the cessation of switching. Our inquiry is specifically regarding when the IVSL current is sampled. The datasheet defines IVSL(STOP) as 80 µA and IVSL(RUN) as 225 µA, but we would like to know the exact timing during the switching cycle at which this IVSL current is evaluated. Could you kindly provide clarification on this point?

Ning Tan said:

Q2: the switching frequency will vary from 170Hz to 30kHz, depending on the load condition.

We are unsure where the 30kHz value originates, but we do recognize that the switching frequency can decrease to as low as 170Hz depending on the load. In our system, false detection on the CS pin tends to occur during startup under light load conditions, where the switching frequency is typically in the range of 25kHz to 30kHz. Our inquiry relates to the diagram on page 16 of the datasheet, which shows that IPP does not fall below 1/4 × IPP_MAX. We would like to know the specific switching frequency (fsw) at which IPP becomes exactly 1/4 of IPP_MAX. From the graph, we can infer that this point lies somewhere between 32kHz and 3kHz, but we would appreciate it if you could provide the exact or typical value.

Ning Tan said:

Q3: The UVLO fault has to be sampled in three consecutive switching cycles before the flyback controller stop switching

Does the term “UVLO fault” refer to the condition defined in the datasheet as IVSL(STOP) = 80 µA?
In SLUAAC5, Figure 8-1 includes the following explanation:

"The Vaux ringing in Figure 8-1 is excessive and rings down below ground during tLK_RESET. This behavior is known to trigger a UVLO fault and shut down the converter. This is because when the VS pin crosses ground it activates input UVLO fault."

As described, excessive negative ringing on the auxiliary winding (Vaux) during the tLK_RESET period may cause the VS pin to drop below ground and trigger a UVLO fault. Could you please confirm whether this UVLO fault refers to the condition where IVSL falls below 80 µA (IVSL(STOP)) and is detected for three consecutive switching cycles, thereby shutting down the converter?

Q5： (Additional question)
We would like to confirm our understanding regarding the parameter "Kvsl = 2.8 typ" listed in the UCC28740 datasheet. Our interpretation is that Kvsl represents the ratio of IVSL(RUN) to IVSL(STOP), serving as a design reference for the hysteresis margin between restart and shutdown thresholds in the UVLO function.
We believe that Kvsl is not directly used in the internal comparator logic for UVLO detection, but rather is provided as a typical design ratio between the two absolute threshold values. Could you kindly confirm if this understanding is correct?

Thanks,

Conor

Hi Ning,

I'm sorry that my comment was insufficient. I'd like to understand it accurately, so could you please comment again?

Ning Tan said:

IVSL(STOP) as 80 µA and IVSL(RUN) as 225 µA refers to VS pin for OVP and input UVLO protection. It has nothing to do with CS pin protection. The CS protection threshold is 1.5V and it is not filtered by LEB. (page 13 in datasheet).

Please read this paragraph for start up sequence.

We would like to confirm our understanding regarding the evaluation timing of the IVSL current (from the VS pin), which is used for UVLO and start-up conditions in the UCC28740.
Our interpretation is as follows:

• IVSL current flows during the period when the MOSFET is ON (DRV = High), and the auxiliary winding polarity clamps the VS pin to GND

• During this time, current flows through the external resistor RS1 and is monitored internally as IVSL

• The IVSL condition is evaluated on a cycle-by-cycle basis, and if the current stays above (for RUN) or below (for STOP) the threshold for 3 consecutive cycles, protection or startup is triggered

• We interpret this as continuous analog monitoring rather than a single, discrete sampling point per switching cycle

Is my understanding above correct?

I would also like to clarify the "timing at which sampling starts" for the IVSL current, so any comments would be greatly appreciated.

Conor said:

We are unsure where the 30kHz value originates, but we do recognize that the switching frequency can decrease to as low as 170Hz depending on the load. In our system, false detection on the CS pin tends to occur during startup under light load conditions, where the switching frequency is typically in the range of 25kHz to 30kHz. Our inquiry relates to the diagram on page 16 of the datasheet, which shows that IPP does not fall below 1/4 × IPP_MAX. We would like to know the specific switching frequency (fsw) at which IPP becomes exactly 1/4 of IPP_MAX. From the graph, we can infer that this point lies somewhere between 32kHz and 3kHz, but we would appreciate it if you could provide the exact or typical value.

I haven't made any comments on the question in Q2 above. Can you please answer it?

I'm very sorry to ask something unreasonable, but we have a meeting with our end customer and it would be very helpful if you could give us your comments by the end of today.

Thanks,

Conor

Hi Ning,

Thank you for your reply. I have five additional questions based on your answer. Could you please answer them?

Ning Tan said:

2) During this time, current flows through the external resistor RS1 and is monitored internally as IVSL

Yes

1). Is it correct to understand that the IVSL monitor is always monitored in an analog manner when the FET is ON (DRV = HIGH)? For example, if the FET is ON for 4 usec, it is always monitored for 4 usec, and if the IVSL falls below 80uA at this time, is it correct to understand that 'IVSL (stop)' is detected once (cycle)? Also, does this analog monitor have a filter time constant for detection?

2). Does the monitoring mentioned in 1) include the Leading Edge Blanking (LEB) period? Or is the IVSL not monitored during the LEB period?

Ning Tan said:

The logic (comparison) will be done at the end of the cycle (when on is end) but the current is continuously compared. 

3). At what moment does one cycle end? Please tell me the specific timing, such as the moment the FET turns OFF, the moment the FET turns ON, etc.

4) In our testing, the oscillation stopped when the CS pin was falsely detected and the FET was turned off immediately after the LEB period. This behavior is unexpected for an IC, but can the IVSL monitor the correct value in this case?

5.) The following is an excerpt from SLUAAC5.

'The Vaux ringing in Figure 8-1 is excessive and rings down below ground during tLK_RESET. This behavior is known to trigger a UVLO faults and shut down the converter. This is because when the VS pin crosses ground it activates input UVLO fault.'

The above "UVLO faults" are IVSL (STOP) = 80uA, but doesn't IVSL monitor when the FET is ON? Isn't the FET off in the above state?

Thanks,

Conor

Hello,

Your inquiry has been received and it will be reviewed in the order it was received.

Regards,

Hi Ning and Mike,

Thank you. I'm very sorry, but due to the development schedule, it would be very helpful if you could answer by today.

Thanks,

Conor

Hello,

Your inquiry has been received and will be answered in the order it was received.

Regards,

Hi Mike,

Your response is very helpful. I would like to know what information customers want to know, specifically the 5 questions I replied to Ning 3 days ago.

Some of these may overlap with the questions in my first post, but I would appreciate it if you could answer these questions.

Thanks,

Conor

Hello Connor,

Thankyou for pointing out there were further questions that needed to be answered.  I will take this one at a time.

1). Is it correct to understand that the IVSL monitor is always monitored in an analog manner when the FET is ON (DRV = HIGH)?

It is looking for IVS to be greater than IVSL (run) for 3 consecutive switching cycles while the FET is on to turn on.

It is looking for IVS to less than IVSL(stop) for 3 consecutive switching cycles while the FET is on.

Please note that if the VS signal is extremally noise the controller can determine the ringing at switching cycles and could turn off the controller.

For example, if the FET is ON for 4 usec, it is always monitored for 4 usec, and if the IVSL falls below 80uA at this time, is it correct to understand that 'IVSL (stop)' is detected once (cycle)? Also, does this analog monitor have a filter time constant for detection?

• If the fet is on for 4 uses and there is not ringing and IVS drops below IVSL(stop) for the consecutive switching cycles the convert will turn-off
• If while the FET is on there is excessive ringing during one switching cycle and the IVS drops IVS(stop) 3 times this will also trigger a fault.
• To avoid issues make sure your aux winding voltage is clean.

I will at the other questions later.

Regards,

Hi Mike,

Thank you for your reply, I appreciate your support. Can you answer any questions other than Q1?

Also, my customer has obtained a waveform based on your advice, so I would like to share it with you along with the circuit diagram information. Since it contains confidential information, is it possible to send it by private message? A friend request has been requested. Or if you prefer email, please let me know your email address.

Thanks,

Conor