TPS6594-Q1: Internal watchdog output

Hi Max,

Max Chen1 said:

Q1: When watchdog time out, EN_DRV goes low, correct ?

Watchdog time out means the device has elapsed the long window time and did not get  expected configurations within time limit of long window. Then in that case MCU can set the ENABLE_DRV to 1  because the MCU can control the logic-level of the EN_DRV pin when the watchdog detects correct operation of the MCU and when the watchdog detects an incorrect operation of the MCU, the TPS6594-Q1 device pulls the EN_DRV pin low. 

EN_DRV can be set in the following situation. 

• When the WD fail counter (WD_FAIL_CNT) value is less than or equal to the configured Watchdog-Fail threshold (WD_FAIL_TH) and bit WD_FIRST_OK=1, the MCU can set the ENABLE_DRV bit when no other error flags are set.
• And when the WD_FAIL_CNT counter value is greater than the configured Watchdog-Fail threshold (WD_FAIL_CNT> WD_FAIL_TH), the device clears the ENABLE_DRV bit, sets the error-flag WD_FAIL_INT, and pulls the nINT pin low.

Max Chen1 said:

Q2: can it be set just a negative pulse output ?

I did not get what do you mean by negative pulse output. TPS6594-Q1 has two WD modes; 1) Triger Mode 2) Q&A Mode. In the Trigger mode, device expects TRIG_WDOG signal on GPIO2 or GPIO11 which are configurable functions for 30µs (typ.) deglitch time period. The voltage threshold level for the trigger pulse is defined in the data sheet by VIL(DIG) = 0V (typ.)   and VIH(DIG)= > 1.26 V , so then that means it cannot be negative. It has to be positive meaning low to high. I hope this answers to your question. 

Max Chen1 said:

Q3: can we re-config a PMIC GPIO pulse output when watchdog timeout ?

I don't think so, WD is supposed to be configured in long window time. 

Max Chen1 said:

Q4: watchdog can be cleared by I2C or PMIC GPIO8, correct ?

I am sorry did you mean disabling the WD ? If yes then my below response can taken for consideration. 

If you want to disable the watchdog then, yes it is possible by the I2C. The MCU can set the WD_EN to 0 and put WD on hold in long window by setting the WD_PWRHOLD to 1. Alternatively, the GPIO8 can be configured for DISABLE_WDOG function which is input to disable the WD monitoring. And  in fact  the TPS6594141BRWERQ1 device , the GPIO8 is configured as DISABLE_WDOG by default. So if you want to disable before the long window e 

Max Chen1 said:

Q5: what is default setting status of watchdog, disabled ?

In TPS6594141BRWERQ1 device, the internal Q&A watchdog is enabled by default and once the device is power up into ACTIVE state, then it can be configured for the trigger if the Q&A is not required.   

See the User guide for all the details : User guide link 

Max Chen1 said:

Q6: can we use watchdog output EN_DRV to reset SoC system?

It is up to the system interrogator of whole system to decide. I can only explain the behavior and what could be expected in what conditions. 

Max Chen1 said:

Q7: how can we get PMICs reset? 

Well reset is possible with different fault conditions. For example, if there is orderly shutdown or  MCU power error OFF request or WDOD ERROR or ESM MCU ERROR etc. See the TABLE-6-1 in the user guide, link provided above. 

Regards,

Ishtiaque 

Hi,

Max Chen1 said:

how much is the long window time?

That means maximum time which is approximately 12 to 13 minutes. 

Max Chen1 said:

I did not mean disable the WD, I meant clear WD timer. we clear WD timer via I2C, correct?

Which WD timer, did you mean Watch do long widow time?

Max Chen1 said:

can you share link of TABLE-6-1?

https://www.ti.com/lit/ug/slvuby7a/slvuby7a.pdf?ts=1744123259947&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTPS6594-Q1 

I gave reference of user guide. See the link 

Max Chen1 said:

I meant logic low pulse, can we config that way?

No right, I already explained this that trigger pulse cannot be configured in that way for the trigger WD. 

Max Chen1 said:

currently EN_DRV goes low right away as long as system bootup, how can I get EN_DRV low immediately if the default is long window 772 seconds by default?

In the long window the EN_DRV goes to low by default. Please see the WD flow diagram in data sheet. 

Max Chen1 said:

Q1:I tried to disable the watchdog via GPIO8 high on TPS6594-Q1, but EN DRV still output low, is there something else I have to clear in order to get EN DRV high? Or EN DRV has to be set high by MCU only, it cannot be high by disable the watchdog ?

The EN DRV needs to be set HIGH by MCU. I have already explained in the answer of first question above.  

Max Chen1 said:

Q2: Watchdog default mode is Q&A mode, enabled, long window , correct?

Yes,  this is written in the user guide. 

Max Chen1 said:

Q3: what is the long window default value: 772 seconds?

This is mentioned above. 

Max Chen1 said:

Q4: can long window value be changed in initialization and new value stored in NVM?

Yes

Max Chen1 said:

Q5: when Watchdog timeout, it will issue a reset on nRSTOUT (pin 25), correct ?

The nRSTOUT is inactive but nINT gets active. 

Max Chen1 said:

Q7: What is the RESET Extension time on Figure 8-20 of page 89 of TSP6594-Q1 datasheet?

This is by default there is certain reset extension needed to be set. For that period the nRSTOUT gets active. 

Max Chen1 said:

Q8: Watchdog Q&A mode does not issue any nRSTOUT when timeout?

Like answered in Q5, It remains inactive after WD timeout. 

Max Chen1 said:

Q9: The datasheet is not clear about signals EN DRV, nINT and GPIO11 (H_SOC_POR-1V8) status when watchdog timeout issues a nRSTOUT low, what are these signals status?

NRSTOUT gets low depending on the fault in sequence. You can see in the user guide that in which sequence the nRSTOUT would set low.

- Ishtiaque 

Hi Chen,

I miss understood, since there is SoC NRSTOUT as well which is configured  in GPIO11. 

But if you meant nRSTOUT (pin 25) , then that is meant to be used as MCU reset or power on reset output . This is Active Low and open-drain configured. 

This would also have the similar behavior as of NRTOUT_SOC signal. Inactive means HIGH and Active means LOW. 

I hope this clears the misunderstanding. 

Regards,

Ishtiaque