• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 136 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS51200-EP: DDR4 VTT and VREF generation -

Garima Dubey
Prodigy 160 points
Part Number: TPS51200-EP
Other Parts Discussed in Thread: TPS51200,

Tool/software:

Hello TI Team, 

For our design we are using micron DDR4 memory MT40A2G8AG-062E AUT:F. 

For the termination, VREF and VTT supply we are planning to use the TI TPS51200 regulator IC. 

www.ti.com/.../tps51200

Our design includes a total of 4x DDR interfaced with FPGA. Address and Control lines are routed in daisy chain fashion, which needs termination on PCB at the end of last memory IC. 

Could we use the the single TPS51200 IC for 4x DDR VREF and VTT termination? 

As per the application DDR4 VDD and VDDQ supply is 1.2V, how to make sure the output from regulator at OUT and REFOUT would be 0.6V exactly? Any calculator or reference design available for DDR4 VTT and VREF generation then please share 

  • 0
    TI__Mastermind 22090 points

    Hi Garima,

    It will depend mostly on the current requirements you need.

    The TPS51200-EP has a sink/source current limit of 3A for the VO output (VO and VTT are the same thing). REFOUT has a 40mA source current limit (REFOUT and VREF are the same thing). You will need to make sure your DDR4 memory won't exceed these limits.

    VO will follow the REFOUT voltage and the REFOUT voltage is defined by a resistor divider to the REFIN pin. The general recommendation is to use 10k resistors with at LEAST 1% tolerance for REFIN accuracy. The specification for VO accuracy was designed to be tighter than the JEDEC requirements but it doesn't list the limits for DDR4 in this document.

    For routing VOSNS, follow the layout guideline highlighted below. If you want to regulate based on the farthest memory unit, you would connect VOSNS to the positive node of the load side capacitors there. A low pass filter is recommended for long VOSNS traces and if capacitance amounts to over 2mOhm ESR.

    Regards,

    James