TPS4810-Q1: PWM frequency

There is a built in delay of 60 us when INP goes LOW -> HIGH. The motivation behind this internal delay is that whenever external FET turns OFF with high current flowing through it, the SRC node goes negative due to wiring harness kickback. If we don’t add this delay then FET will remain ON even if it commanded by device to be turned OFF. This delay ensures robust turn OFF of external FET. 

As you go higher in frequency, max duty cycle will come down.

For Ex: if frequency is 3kHz (333us) then max achievable duty cycle is ~82% (333us-60us)/333us across temp.

 Thanks,

Sarah