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LMG2100R044: Will both GaNFET become Hi-Z?

Kei Kuwahara
Expert 7660 points
Part Number: LMG2100R044

Tool/software:

Hello team,

My customer is considering LMG2100 for buck converter.

However, they are worried if both high side and low side GaNFETs are OFF, then the SW node will be Hi-Z, therefore the inductor current will cause very high voltage.

Question1
Will SW pin of LMG2100 be Hi-Z in any condition except for dead time?
Customer is worried what would happen if VCC is suddenly lost during operation. Will that condition turn off both of the GaNFETs and SW become Hi-Z?

Question2
Are there any protection feature to prevent from SW node becoming Hi-Z?

Some of our UCC gate driver product opens the Low side FET to prevent Hi-Z state.

Best Regards,
Kei Kuwahara

  • +1
    TI__Expert 4935 points

    Hi Kei, 

    Kei Kuwahara said:
    Question1
    Will SW pin of LMG2100 be Hi-Z in any condition except for dead time?
    Customer is worried what would happen if VCC is suddenly lost during operation. Will that condition turn off both of the GaNFETs and SW become Hi-Z?

    The LMG2100 can be thought of a standard FET half-bridge in this scenario. When there is no input applied to the LI pin, the low-side FET is in the off-state and it's resistance is typically 8Meg Ohms, according to the datasheet leakage current paratmer, IL-SW-GND. If VCC is lost during operation, the FET will turn off. This means that yes, the SW pin will show high-Z in any other condition aside from LI pin is high or the FET is operating in third-quadrant conduction (dead-time conduction). 

    Kei Kuwahara said:
    Question2
    Are there any protection feature to prevent from SW node becoming Hi-Z?

    There is no feature that this device has to prevent Hi-Z when there is no HI or LI input to the FETs. I don't necessarily understand why this would be a concern though. In a CCM buck converter with always-positive current, the body-diode (for GaN FETs, it's the third-quadrant conduction mechanism) of the low-side FET always provides a path to conduct the inductor current. Of course ringing will always be observed on the SW pin when the low-side FET is turned off due to high L*di/dt event, but this is unavoidable with any device. 

    Kei Kuwahara said:
    Some of our UCC gate driver product opens the Low side FET to prevent Hi-Z state.

    If the low side FET is open, it would be in a Hi-Z state, not low-Z state.

    Thanks,

    John