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TPS543C20A: TPS543C20A,PSPICE,Stackable simulation

Part Number: TPS543C20A
Other Parts Discussed in Thread: TPS543C20

Tool/software:

Hello,

Does Pspice model SLUM671.ZIP  for TPS543C20A  support stackable mode? 

  • Hi Cheong, 

    We typically simulate a stacked design by simulating a single rail with half the total cout and half the load current.

    Let me know if this works for you

    Best regards,

    Britton

  • Hi Britton,

    Thanks for your prompt reply. Not fixed it at my bench. Simulation result not met my expectation.

    It seems to be enter into fault when inductor ripple became over 50A , and something weird when modified the Rload or replace it to another type.

    Could you release stacked simulation dsn as an official for TPS543C20A?

  • Hi Cheong, 

    What is the use case here? Are you just simulating TPS543C20A to get an understanding of its performance in stacked mode under a certain condition? 

    Since stacked devices share half the output current. We typically use a single device, set in standalone mode, with half the output current and the half of the total output capacitance to simulate the device's stacked behavior - this should simulate without any issues. There are not currently any plans to release additional TPS543C20A models

    Best regards,
    Britton

  • Hi Britton,

    My purpose must be simulating stacked mode before tape out of my stacked design.

    Anyway, I think TPS543C20A has an issue on MODE control.

    From the datasheet, 15.4k,121K ,181K,8.66k,78.7K are also one of stand alone mode. 

    Based on my experiment, it works only on API off/BB off mode. 

    Would you confirm whether MODE works or not?

    Thanks,


    Cheong

  • Hi Cheong, 

    API/BB is not implemented in PSPICE, but 2-phase stackable MODE options are implemented. There are 2 ways you can model stacked configuration:

    1. As mentioned above, the simplest way to model a stacked configuration is to simulate a single device with half of the output current and half of the output capacitance. This models the device performance in a 2-ph configuration

    2. Using 2 devices, here is an example test bench and simulation results for 2-ph stacked mode

     Pages from TPS543C20_PSPICE_TRANS_Report.pdf

    Best regards,

    Britton

  • Hi Britton,

    Thaks for your kind reply. I had tried to simulate with 2nd way, hasn't fixed yet.  whatever i tried at lower I load, current reached to ~50A at inductor. When reached to >50A at inductor, immediately looks shut downed.

    From your results, I couldn't clear undertand below.

    Q1.  My downloaded component moded from slum671.zip looks TPS543C20ARVF_TRANS. your pdf indicated it as TPS543C20_TRANS. Are they same model.

    Q2. Rise time of V2 which is power source is 2ms in your model. Simulation result looks source reached to 12V at 500us. and, turned on after 600us. It seems to be results and simulation circuit doesn't matched. 

    Anyway, I tried to turn on the TPS543C20 after saturation of power source. Result wasn't my expectation.

    Below is my siumation results. As you seen, current at L reached to >50A whatever I adjusted the slew rate and I load. And then, shut downed.       

    Q3. From the datasheet, Figure 33 described master only sense the Vout. Your example described both master and slave sensing the Vout through RSP and RSN. Which one is correct?

    Thanks,

    Cheong

  • Hi Cheong, Allow me some time to check on the model to make sure the online model is the latest. In the meantime, please use option #1 to simulate the expected performance of a 2ph design using a single device.

    For Q3) Connecting to slave RSP/RSN is not required in stacked configuration, you can find a similar exampe to the datasheet here: https://www.ti.com/lit/ug/sluubl7a/sluubl7a.pdf?ts=1744391154282&ref_url=https%253A%252F%252Fwww.ti.com%252Ftool%252FTPS543C20EVM-869 

    Best regards,
    Britton