UCC28064A: About Rzx, Ra, Rb, and Rt settings

Hello Takahara-san, 

Here are my replies to your questions:

(1)  The purpose of Rzx is to limit the maximum current into or out of the ZCDx pins.  The absolute maximum rating for ZCDx current is +/-5mA, and it is recommended to target less than that for reliability.  In the UCC28064A datasheet, Section 9.2.2.3 (page 39), a target of 3mA is used in equation (25) for calculation of the appropriate minimum resistance.  Note that the ZCD winding turns-ratio was determined using equation (24). 

The value of Rzx can be higher than the minimum that is calculated, but too high of a value can lead to timing turn-on delays that may result in missing pulses at high-line peaks or near the zero-crossings.  Part of the ZCD circuit includes the ZCD capacitors (CZAX and CZBX in your design), which are discussed in Section 8.3.5 (page 17).  If Rzx is increased without decreasing CZxX, the ZCD timing may be slowed down too much and the ZCD voltage may not reach the 1.7V arming threshold when the MOSFET on-times are very short at the peaks of high-line.  If the ZCD circuit is not re-armed to trigger the next switching cycle when Vzcdx falls below 1V, switching will stop until restarted by the 210us restart timer.  
This may be what is causing the output voltage fluctuations at start-up when Rz = 136kR.
 
It is interesting that you found that THDi can be improved with higher values of Rzx.  Assuming that you did not change CZxX, the additional time delay may be having some unforeseen beneficial effect on THDi.  That is worth exploring further to understand it and take advantage of it, provided that the additional delay does not result in missing switching pulses. 

(2)  The impact of low values of Ra and Rb is that no-load stand-by power loss is increased.  The consideration is simply a matter of how much power loss is acceptable in the VINAC divider network.  The same consideration goes for the VSENSE input resistor divider values. 

The purpose of capacitor CINACX on the VINAC input is to filter high frequency noise from the VINAC signal.  Ideally, there is no noise and CINACX is not necessary.  Realistically, there is some noise and some amount of filtering may be necessary.  Empirical evaluation in the past has shown that the R-C time constant for VINAC filtering should not exceed ~100us.   Since the value of Ra is usually much higher than Rb, Rb effectively sets the time constant with CINACX.  Therefore, CINACX </= 100us/Rb, for any value of Rb.  The same consideration (and same 100us time constant) applies to the VSENSE network.

(3)  The purpose of Rt is to set the maximum allowable on-time, which indirectly sets the maximum output power that can be delivered.  
In the UCC28064A, higher values of Rt result in lower maximum output power, so that full power may not be available at the lowest input line voltage.
Conversely, lower Rt results in higher max power capability, which may allow excessive output power in an overload condition.  

The correct value of Rt is normally determined at maximum desired output power and at lowest input voltage.   
Section 8.3.3 (page 16) discusses the effect that the TSET resistance has on the on-time, but Section 9.2.2.9 (page 42) details how to calculate the correct value.  Equation (46) determines the correct maximum on-time, while equations (47-49) determine the correct resistance for Rt to obtain that on-time. 
 
Equations (48) and (49) account for the effects of voltage feed-forward by VINAC where the (5V)^2 term in eqn (48) corresponds to 265Vac input and the (1.6V)^2 term in eqn (49) corresponds to 85Vac input.  The lower of the two Rtx is the correct value for Rt.  

Yes, it is correct that KTH_min is 0.36us/V and KTL_min is 3us/V. 
The 133kR term in the equations is an internal timing constant.
4.825V is the maximum voltage that COMP has when Vcomp is clamped to 4.95V (per equation (4): ton = (Vcomp -0.125V)*Kt).  When Vcomp = 4.95V clamp,  (Vcomp -0.125V) = 4.825V.  

Rt has a minimum value of 66.5kR.  This resistance generates a current within the IC which is mirrored to several sub-circuits.  Lower Rt would generate higher internal current which can saturate these mirrors and lead to unpredictable timing and possibly overstress the metallization or devices in some of these subcircuits.  Please do not reduce Rt value below 66.5kR.

Once Rt is set for max power at 85Vac, it should work for all voltages higher than that... 115Vac, 220Vac, 264Vac.  
There is no expectation that Vout would dip to 360V for 220Vac only, yet regulate to 400V at all other voltages.  
I believe that some other problem is causing that voltage dip at 220Vac, possibly noise affecting VSENSE, or incorrect ZCDx inputs, or something else.
Somehow, the poor-regulation effect is mitigated when Vac goes higher than 220V again.    
I believe that this is not an Rt issue and the true cause of the dip should be discovered and corrected.

Regards,
Ulrich

Hi Takahara-san, 

(2) In my experience, I prefer RC< 100us.  160us can still work, but the higher the filter time constant, the slower the reaction to changes. 

For VINAC input, the zero-crossing detection is important for the Line Dropout Detection feature with a threshold at 0.35V.
Too much filter capacitance will smooth-over the zero-crossings and VINAC may not reach down to 0.35V, for example.  The Line Dropout feature will be defeated and high peak input current may result after the drop out ends.

For VSENSE input, reaction to load steps will be delayed and Vout can drop lower than expected. 

My original statement is correct: "Therefore, CINACX </= 100us/Rb, for any value of Rb."  This is based on my statement just ahead of it: "Since the value of Ra is usually much higher than Rb, Rb effectively sets the time constant with CINACX."   As long as Ra >> Rb, CINACX </= 100us/Rb, for any value of Rb.

(3) Rt has no long-term effect on Vout.  In steady-state, output voltage is regulated by the voltage loop comparing VSENSE to the internal 3V reference.   
In transient conditions, there may be a temporary overshoot of small magnitude above the nominal Vout, but regulation is restored within 100 milliseconds or so.  Mild OV is limited by the OVP1 protection, while gross OV is limited by the OVP2 protection.  
Rt too high reduces max on-time and lowers output power. 
Rt too low reduces max on-time and allows higher output power.  During a transient condition (such as a line-step) the slow V-loop can temporarily allow higher output power which raises Vout until the V-loop can adjust COMP voltage lower to regain regulation. OVP1 action keeps Vout from going too high.

For equation (48), I believe that it is correct as written, but I am not sure.  Like you, it seems to me that maybe (48) should use VIN_MAX to be consistent with the Kth and (5V)^2 terms, but I think the derivation is more complicated than meets the eye.  I'll have to investigate this.
But I think it is correct because the Rt value with VIN_MAX would be about 1/10 of the existing result, and I think we would have gotten many complaints of bad designs.

Regards,
Ulrich