LM5050-1: About Gate off timing

Hi All,

Additional questions:

Is it possible to calculate the IGATE(OFF) current when the gate has a 10 Ω resistance?
Please tell me the calculation formula.

Hi Tamaki,

The turn-off time can be calculated by using the gate pull-down strength and MOSFET Ciss with the general capacitor equation. (I=Cdv/dt)

Regards,

Shiven Dhir

Hi Shiven, 

Thank you for your cooperation.
The calculated value does not match the actual measured value, so please let me know if there are any other factors that may affect the calculated value.

When I calculate the peak current under the conditions below, it does not match the actual measured value.

Ipeak = Vgs / Rg
　　　= 4.32V / 10Ω
　　　= 432mA

Measured value = 324mA

[Conditions]
Ciss=5880pF
Vgs=4.32V
Rg=10Ω
t=180ns

I think this is due to the internal resistance of the LM5050.
Please tell me the value of the internal resistor during forward to reverse transition and OFF pin low to high.

And, I would like to see a concrete example of the calculation.

Hi Taramki, 

I will check this with designer and confirm it to you.

Regards,

Shiven Dhir

Hi Tamaki,

From the datasheet spec, the typical value of the resistance is around 1.2ohms.

It can range from 1.7 - 1.2 ohms

Regards,

Shiven Dhir

Hi Shiven, 

What is the equation that gives the solution 1.7-1.2 ohms?

Hi Tamaki,

It comes from V/R equation. According to datasheet, the typical current is 2.8A at VGS of 3V. Minimum Current is 1.8A at 3V.

Regards,

Shiven Dhir

Hi Shiven, 

Thank you for your answer.

Is the internal resistance the same at time forward to reverse transition and OFF pin low to high?

Hi Tamaki,

The resistance should not change.

The data sheet says "Unless otherwise stated the following conditions apply: V IN = 12 V, V VS = V IN , V OUT = V IN , V OFF = 0 V, C GATE = 47 nF, and T J = 25°C."
But is it okay to use 3V for VGS?

Hi Shiven, 

In the block diagram on the data sheet, it looks like the FET is driven after the OR circuit, but I think the driving conditions for the FET are different.

The current waveforms taken in our circuit have current values ​​at forward to reverse transition and OFF pin low to high that result in different FET driving conditions.

Hi Shiven, 

We confirmed different shape of gate sink current.

Between off-port control and VSD reverse shutdown.

Question

 Are there  any different of gate drive of   2A MOSFET ?

 for ex )

Hi All,

I would appreciate it if you could reply by tomorrow.

Best regards, Tamaki

Hi Tamaki,

TI India is on a holiday today. I will get back to you by Monday.

Regards,

Shiven Dhir

Hi Tamaki,

I checked the results with designer. The feedback is as follows.

The results shared are not comparable because the VGS voltages are different.

This VGS voltage results in difference in the resistance of internal FE switch.

It is recommended to test with comparable VGS. Say VGS = 100mV or VGS = 8V.

Regards,

Shiven Dhir

Hi Shiven, 

Thank you for your confirmation.

You replied that MOSFET Ciss can be calculated using the general capacitor formula (I=Cdv/dt), but does that mean it cannot be calculated?

Hi Tamaki,

It still holds true, since customer has added a 10ohms resistor, this equation will not told true. 

Regards,

Shiven Dhir

Hi Shiven, 

I will rephrase the question again.

To verify the validity of our circuit, we want to calculate the gate discharge time for reverse shutdown (tGATE(REV))
and off terminal control (tGATE(OFF)) when the gate resistor is 10 Ω.

Question
What is the formula for calculating tGATE(REV) and tGATE(OFF) when the gate resistance is 10 Ω?

Best regards, Tamaki

Hi Tamaki,

Formula can be calculated once we find out the current flow into IC with 10ohms resistor.

Please help repeat the experiment with VGS=8V with OFF pin and reverse current conditions.

Regards,

Shiven Dhir

Hi Shiven, 

Since we want to verify the validity of our circuit, there is no point in performing an experiment with VGS=8V.
I understand that the specifications are the representative characteristics, but when VIN = 12V, VGATE = VIN + 3 V.

Q1. Where do the values ??VGS=100mV, VGS=8V come from?

In our circuit, the current flowing through the 10 Ω gate resistor is measured as shown below,
so we think it is possible to calculate tGATE(REV) and tGATE(OFF).
I would like to know the formula for calculating tGATE(REV) and tGATE(OFF).

The specifications state that tGATE(REV) max: 350ns, tGATE(OFF) typ: 486ns.

Q2. Could you please tell me the formula and conditions to calculate a value close to this?

OFF control
VGS voltage: 3.44V
GATE current:148mA

Reverse shutdown
VGS voltage: 4.32V
GATE current:324mA

[Conditions]
FET Ciss:5880pF
Rg:10Ω

Hi Tamaki,

VGS = 100mV and VGS =8V are an example values of GATE in which you should be able to equal turn-off currents. Basically, the idea was to keep the VGS equal in both the cases.

Reverse Current:

The datasheet states a typical turn-off time of 180nS during reverse current condition.

This also talks about the condition of VIN-VOUT transition that is 200mV to -500mV. 

200mV means the GATE is fully enhanced and VGS is ~12V and is measured till VGS is 1V. This means difference in voltage of GATE is 11V.

This can be justified with the I=cdV/dT equation.

2.8A = 47nFx(11)/dT ~185nS which matches the 180nS spec.

OFF:

tGATE(OFF) will have certain amount of propagation delay as well.

Note: These equations are valid for a constant pull down source whereas in reality we see a peak pulse of current and turn-off time should come little higher.

Regards,

Shiven Dhir

Hi Shiven, 

Is it possible to calculate that the turn-off time becomes little higher when using OFF control?

What elements are required for the calculation?

Best regards, Tamaki

Hi Tamaki,

OFF pin has an added propagation delay. Rest, the entire calculation remains the same.

Regards,

Shiven Dhir

Hi Shiven, 

What is the maximum propagation delay when controlling the OFF pin?

Best regards, Tamaki

Hi Tamaki,

I will check with designer and get back to you by friday.

Regards,

Shiven Dhir