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TPS65219: Questions about the default setting for TPS6521910

Rich Chen
Expert 4170 points
Part Number: TPS65219

Tool/software:

Dear Champ, 

Customer reviewed TPS6521910RSMR TRM, there are some NVM default settings regarding PMIC ON/OFF control and RESET need further clarifications as followers.

 

  • Pin-25 “EN / PB / VSENSE”

  • Why this pin be config to push button as default?
  • Any specific applications that AM67x focused need push button for power ON/OFF controlling by manual operation (press and hold 600ms)?
  • FSD be enabled as default. Does it mean PMIC will AUTO power ON without long pressing bush button once power valid first time?
  • If sudden power loss appeared during power ON procedure, any backup mechanism for fail recovery to prevent PMIC stuck?
  • Is it possible to re-program this pin to be EN as default?
  • If this pin be config to EN as default, then EN be transient from HIGH to LOW would enable PMIC internal discharge circuit (supposed it had) on each power rails or not?

 

  • Pin-28 “MODE / RESET”

  • Why this pin be config to WARM reset rather than COLD reset?
  • Any side effect once modify this pin to be cold reset as default?

 

  • TPS6521910RSMR NVM write operation or re-programming
    • NVM can be re-program multi-times or not?
    • Is it possible to modify NVM default setting upon programmed PMIC?
    • If we want to partial modify NVM default settings via software command, then this modify or change still be valid or not after power cycling?

BR, Rich

  • 0
    TI__Expert 6245 points

    Hi Rich,

    - I need to find out the reason behind configuration to PB.

    - yes, when FSD is enabled, PMIC will ignore EN/PB on the first power up and as soon as VSYS ramps up, PMIC starts to power up.

    - If the power up sequence is not complete, PMIC will initiate a power down sequence and pull down on the output rails will be engaged to discharge the outputs.

    - Yes, thru NVM programming, it can be changed from PB to EN.

    - Correct, when EN goes high to low, it will start power down sequence and discharge resistors are engaged.

    - Since it would be a warning only, we just want to keep the rails at the same voltages.

    - Cold reset will cause the PMIC to sequence down all the rails and power up again.

    - Yes, since NVM is EEPROM, this can be programmed multiple times.

    - Correct, all the user accessible NVM can be programmed.

    - In order for the NVM to store the values, those need to be burned into the device and upon next power cycle, the device will default to the new values.

    Sathish

  • 0 in reply to Sathish Vallamkonda
    Prodigy 60 points

    Hi Sathish,

    1. Any update of PIN-25 be PB as default setting?

    2. In theorem, cold reset will have better false recovery comparing with warm reset due to full power cycle be done properly. If internal state machine be stuck and all power rails still be kept, then it may be suffered boot up fail once again.

    3. Owing to FSD in NVM default be enabled upon programmed PMIC, it should go power ON procedure once power supply be valid rather than NVM programming process. In this situation, IN CIRCUIT NVM re-programming is workable or not?

    4. If not, any suggestion to make it works?

    Regards,

    Jones

  • 0 in reply to Jones Hung
    TI__Expert 6245 points

    Hi Jones,

    1. i am not sure about why it was chosen like that, may be requirement from SoC.

    2. For AM62x only required a warning so it was set to warm reset.

    3. When FSD is enable, PMIC will initiate the power up routine as soon as VSYS reaches expected voltage. And, NVM can be changed after that.

    Sathish