Tool/software:
Hi Team,
I would like to check the meaning of the following sentences
8.3.5.8 Power-Up and Power-Down Behavior:
in case the VDD power supply is enabled the first and the VDD voltage exceeds VDD,UVLOR before the VS supply is up and VS voltage exceeds VS_UVPR, the outputs remain disabled.
If that mean if VDD power up first and VS don't power up ,the output will disable, once when the VS > UVPR, output will be active. If my understanding correct?(This means that there is no timing requirement for VDD and VS, when both VS and VDD higher than the UV, device will be active)
Thanks!
Jenson
