UCC14141-Q1: Isolated DcDc module activation

Hi Manual,

For pt.2, the TI website link is given below

https://www.ti.com/lit/df/tidmai7/tidmai7.pdf?ts=1744305955915

I will work on other points and let you know the outcomes.

Thanks,

Sridharan

Regarding the load condition for UCC14141-Q1, you can see from the schematic that UCC21755 is the load and I am not supplying any PWM.

Ok, please provide the waveforms to check for any faults.

Thank you

For pt.1, the resistor divider is connected between VDD and VEE. Total voltage across these two will be 15-(-3) = 18V. So the top resistor value has to be 62k to get 15VDD. If I change to 50k, I would get 3V which is above the value given in the datasheet. Please see screenshot.

Hi Manuel,

I have noticed that there is no output from the 12V-5V LDO. Part number is TPS7B8650DQDDARQ1. 5V output with 500mA current capability. This LDO supplies 5V to both the DcDc module and the Gate driver chips. Please see its schematic diagram screenshot below. When I supply 12V to this regulator, its not producing 5V. I built a breadboard-power supply of this chip which seems to be working correct. 

From the gate driver datasheet, I read the Quiescent current is not more than 4 mA on VCC side. 

Quiescent current of the DcDc module is not more than 40mA at no load. 

So this confirms that the 5V LDO is not at all loaded. 

Can you review the circuit and let me know your comments.

Thanks.

I post the observation on the LDO in this post because it is related to the design and not just for the part.

Thanks for the understanding.

Steps followed:

1) Set appropriate trigger values 

2) Turn on Vin = 12V

3) Turn on V-EN = 5V

VDD-VEE

VDD-COM

COM-VEE

PG-GNDP

I have noticed that 12V-5V LDO not giving any output. So I supplied 5V externally and observed the above. 

It will be really helpful if you can review and comment at the earliest.

Thanks.

Hi Sridharan,

Manuel is OOO for a few days so I'll try to help here.

It looks like you're getting a fault on startup. Please capture startup waveforms similar to those in sec 5.4 & 5.5 of the EVM User Guide. Note the voltage and time scales.

So that we are on the same page, please upload a completed Calculator Tool.

Since layout is very important, please provide images so we can review. Be sure to include each layer around the UCC14141 and all associated components. Ref. section 9.5 in the datasheet.

Regards,

Ray

Hello Ray,

Please find the completed calculator tool with the design values we use currently.

Images of the board layout is given layer by layer.

I will work on further to capture the waveforms as in the EVM manual and share at the earliest.

I will be traveling in the coming week, so my responses will be delayed. 

Thank you,

Sridharan 

UCC14141-Q1_Calculator_V8.xlsx

Sridharan, thank you for the completed calculator tool and for the excellent board images. I look forward to seeing the startup waveforms.

After you collect the first set of waveforms using the LDO, please recollect using a bench supply for +12Vin set to it's maximum current limit (none).

Tomorrow is a holiday for TI so we will pick this up again on Monday. 

Ray

Uploading the first waveform as given in Section 5.4 of the UCC14141EVM-068 page #14. 

Since I have built the prototype, the gate driver has been directly connected to the VDD line. So I cannot apply I(Vdd-Vee) = 68mA. Please advise.

Thanks,

Sridharan

Uploading a better image.

Shutting down at 24.8 mSec.

It looks like you're getting through startup.

Please label your signals (or just tell me what each color goes with what signal).

I don't need Ivdd-vee, just Ivin is fine for now.

It may also help to capture the following signal:

I'll look at everything on Monday.

Have a great weekend!

Ray

Hi Ray,

Captured the Vin and PG waveforms. Added labels. 

Hello Steve,

Attached the schematics of the design with the capacitors highlighted on the HV side. Their values are 10uF and 0.1uF on every leg. I haven't maintained the output capacitors ratio as you have mentioned. 

I am currently in travel so I cannot physically make the corrections on the prototype. You can refer to the calculator tool I have posted above as well.

Thank you,

Sridharan

I have asked my colleague to measure the output of the FBVDD and FBVEE resistor divider midpoints. He measured the voltages as FBVDD= 2.7V and FBVEE= 8.74V. The FBVEE is above the OVP limit on that line which is not satisfying one of the Power Good pin conditions. FYI.

Thank you,

Sridharan

Checked the resistor divider values, they seems to be correct.

The /PG pull up resistor has been replaced by 5.2k resistor.

The capacitor values are as follows. I understand that they are the biasing capacitors for the gate driver chip.

C16, C18, C23 = 10 uF, 35V 

C17, C19, C24 = 0.1 uF, 50V

Additionally, the following capacitors added across Vdd-Vee, placed close to the Vdd pins of UCC14141; 

C1 = 0.1 uF, 35V 

C2 = 10 uF, 50V

I am using a single RLIM resistor circuit for the dual adjustable power output. Do you recommend to go with two RLIM with a diode configuration? 

Thank you.

I am back and did this math. VDD*CVDD=VEE*CVEE

VDD*CVDD = 15 * 10.1 = 151.5

(VDD*CVDD) / VEE  = 151.5 / 3 = 50.5.

So I selected 47uF capacitor and placed at across Com-Vee (C23) and got the following waveform.  

It seems the Dc-Dc module is working now. But when I put on the capacitor values on the calculator (excel) tool, the value of Cap across Com-Vee is just 11uF.  Screenshot below.  Please advise. 

Thanks a lot!

Today, I supplied a 100 kHz PWM signal to the gate driver. The DCDC module shuts down at the start of the PWM signal. Is there anything should I check on the gate driver? 

1. VIN is not dipping below the input UVLO.
2. VDD-VEE (FBVDD<2.25V) is going to 0V because the DCDC module is shutting down.
3. COM-VEE (FBVEE<2.25V) is going to 0V because the DCDC module is shutting down.
4. Increased the VDD-COM capacitor value from 2.2µF to 10.1µF and VEE-COM capacitor from 22µF to 100µF per the excel sheet tool.
   1. VDD-COM caps (C16, C17) and VEE-COM caps (C23, C24) are placed close to the gate driver.
   2. VDD-VEE caps (C1, C2) in placed close to the DCDC module. C18 and C19 are additional caps across VDD-VEE placed close to the driver.
5. Regarding RLIM value, the excel sheet calculator shows 157.5 Ohm for the above new cap values. So I placed 150 Ohm resistor. 

With these changes done, the DCDC module is still shutting down for a 100k PWM signal. 

Regarding RDR configuration, will have to check with my team as they are more focused on the functionality rather than improving the efficiency.

Thanks!

Sorry I didn't understand the question. Are you asking about connecting a resistor at the gate driver output?

Noted. While I start to work on this one, I would appreciate if you can review the input side schematics of the DcDc Module and the gate driver circuitry as there are RC filters exist. Please check if these filters contribute to the premature shutdown. Thanks.