Other Parts Discussed in Thread: TPS7A7200, TPS7A57, TPS7A85
Tool/software:
My team is working on some designs using the TPS7A85A. We intend to use them to power the multiple rails of an FPGA. Each rail on the FPGA has its own capacitance requirements based on utility. Regarding part selection, we saw the startup control and output current to our benefit, and was an upselect from a 2A TPS7A7200.
I have been using the unencrypted model in LTSpice for each of the design simulations to run worst case analysis - as best we can. It was noted in the model file that temperature effects are not modelled. For me it is easier to run LTSpice over the PSpice tool to get the performance envelope plots.
That said, I have noted an artifact that appears within the first 100us of the whole simulation. It appears as a current spike transferring from input to output despite the input voltage to the device still remaining very low (<50mV) during its ramp up. This spike is rather narrow at about 75ns wide. This pulse magnitude is dependent on the input to output voltage, input capacitance, output capacitance and related ESRs, and possible plane/trace resistance on the as yet to be designed board. This current can exceed the 4A stated current limit in the datasheet, and can reach apparently the internal IC current limit at about 5A.
I took the time to run the model in PSpice for TI with the associated files in the encrypted model, modified to resemble my application to see if this was tool related. This same spike event appears. My guess here is that the internal pass transistor capacitance is transferring current through the device as soon as sufficient charge is in in the device and placing a charge on the output capacitors, despite the ENABLE pin held low. I can see the output voltage ramp up during these events.
My objective at this point is to factor in reliability in the design by derating the overall current on the output pins at any point in time to less than the device max. This artifact would limit MTBF as it imparts an overstress condition. So, is this artifact something that is simulation related, or will it be present in the actual design?
Our overall current requirements on each rail is well within the general limits of this part. However I'm concerned about the artifact potentially overstressing the IC, even though the event is very short. Prior to committing to design, are there some options here that we can consider other than adding duplicate parts for redundancy, or moving to a different part?
Thank you.
