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UCC27710: Effect on adjacent terminals

Shuji Ishiwata
Mastermind 7845 points
Part Number: UCC27710
Other Parts Discussed in Thread: UCC27714

Tool/software:

Hi All,


I have a question about the UCC27710.

Is there any documentation that shows the effect on LO (5 pin) when 620 V is applied to HS (6 pin)?

I would like to know if there are any reasons or indicators that show that the insulation space between pins is not a problem.


Best Regards,
Ishiwata

  • 0
    TI__Mastermind 23155 points

    Hello Shuji.

    Thank you for your interest in the UCC27710. Your question is a common question on the 8 pin SOIC 600V drivers regarding the pin spacing. There are several factors that apply specific to the application, regarding spacings of traces. Most applications do not have working voltages that are at the IC ratings is one consideration. In many cases the ap-plication is much less than the driver rating and the actual voltages are not a concern. In other cases the application will require that a coating is applied to the board and components, which reduces the required spacing. This concern will exist with any 8 pin SOIC high voltage half bridge driver, as there will always be a low voltage or ground pin close to the high voltage pins.

    Regards,

  • 0 in reply to Richard Herring
    Mastermind 7845 points

    Hellow Richard,


    Thank you for your reply.

    The customer is planning to use it for PFC control.

    Do you have a reference circuit for UCC27710 for PFC control?

    In your comment, you said that the IC rated operating voltage will not occur,
    Is it possible to provide a customer with a reference PFC circuit that does not actually cause any problems?


    Best Regards,
    Ishiwata

  • 0 in reply to Shuji Ishiwata
    TI__Mastermind 23155 points

    Hello Ishiwata,

    Can you confirm the PFC topology that the customer is considering? Is it the totem pole PFC? My comment was based on in some applications the voltage stress on the driver is not at the full IC rating, but it is application dependent. Is the PFC output voltage 400V?

    Regards,

  • 0 in reply to Richard Herring
    Mastermind 7845 points

    Hello Richard,

    Thank you for your reply.

    A customer is considering a totem pole PFC.

    Best Regards,
    Ishiwata

  • 0 in reply to Shuji Ishiwata
    TI__Mastermind 23155 points

    Hello Ishiwata,

    I looked at some basic information on recommended spacings. and it depends on the standard target.

    PCB Trace Spacing Calculation for Voltage Levels

    For 400V uncoated boards it looks like the recommended spacing is ~1.4mm or beyond. There is another 600V driver in the SOIC14 package which has much higher spacing on the high voltage pins. You may want to look at the UCC27714 600V half bridge driver if higher spacing is desired.

    Regards,

  • 0 in reply to Richard Herring
    Mastermind 7845 points

    Hello Richard,


    I am very grateful for your answer.

    A customer is considering adopting UCC27710.
    Is there any reference document for the reference circuit of UCC27710 for PFC control?


    Best Regards,
    Ishiwata

  • 0 in reply to Shuji Ishiwata
    TI__Mastermind 23155 points

    Hello Ishiwata,

    I am not aware of a PFC ti reference design using the UCC27710. But I did find a reference design with a similar 600V driver, the UCC27714 for a totem pole PFC design.

    https://www.ti.com/tool/TIDM-02008

    I hope this helps. Both drivers are 600V half bridge drivers.

    Regards,