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TPS25751: Patch Load via I²C Host – Stuck in Boot Flags 0x05

Part Number: TPS25751


Tool/software:

Hello,

I'm working on a project involving the TPS25751, and I’d appreciate assistance confirming or correcting our approach for patch loading via I²C host controller (STM32).

Setup Overview

  • TPS25751D powered from VBUS (USB PD Source input)

  • No EEPROM connected

  • Using STM32G070 as I²C host

  • Patch generated using TI Application Customization Tool (exported .json, .c, and .bin)

  • I²C communication confirmed working at address 0x20 (SafeMode)

  • Using target I²C pins for patch delivery (not controller I²C)

  • ADCIN1 = 3.3V (code 7), ADCIN2 = GND (code 0) → SafeMode + I²C address #1

What Works

  • TPS25751 is detected after boot (Boot Flags = 0x05, Mode = 0x04)

  • I²C patch delivery works:

    • Patch array is EEPROM-style: sent from address 0x00 in 16-byte blocks

    • All bytes are transmitted successfully (confirmed via debug print)

  • Read registers after patch load:

    • Boot Flags = 0x05

    • Mode = 0x04

    • But never enters Boot Flags = 0x07 (APP mode)

What’s Not Working

  • TPS never jumps to APP mode even after full patch load (0x1E00 bytes)

  • Tried multiple patch formats: full flash (.c, .bin), low region only, known-good test arrays

  • Implemented PBMs protocol:

    • Wrote 7-byte bundle descriptor to DATAx registers

    • Wrote CMD1 = 0x01 to initiate PBMs

    • TPS responds with CMD1 = 0x04 consistently (command rejected)

    • DATA1 always shows error (not 0x00)

  • Verified that:

    • I²C address = 0x20

    • Patch size is correct (7680 bytes)

    • Timeout is reasonable (0x20 = 3.2s)

Could you please confirm the correct procedure to load a patch via I²C host in SafeMode for the TPS25751?

Specifically:

  1. Is there an official .bin or .c export format that is guaranteed to be I²C-host loadable, with APP jump entry?

  2. Is PBMs required, or is EEPROM-style I²C load from 0x00 sufficient in SafeMode?

  3. What exactly does CMD1 = 0x04 indicate during PBMs?

  4. Can you provide a minimal .bin or .c patch bundle for SafeMode testing that is verified to reach Boot Flags = 0x07 via I²C?

We would like to load the patch from STM32 on every power-up, without needing external EEPROM. Your help confirming the steps (or providing a known-good patch) would be greatly appreciated.

Thank you for your time and support,

Regards,

Sergey

  • Hello,

    Please find the attached.  

    /cfs-file/__key/communityserver-discussions-components-files/196/cobraPlus_5F00_PMBs_5F00_DBFg.csv

    It appears that the system is not supplied via VIN_3V3 even after the update has taken place, so do not clear the dead battery flag as this will cause the PD to attempt to power from VIN_3V3.

    Could you please confirm the correct procedure to load a patch via I²C host in SafeMode for the TPS257

    The attached example is taken from the EVM and uses the alwaysEnableSink.  I do not have an example for safemode.

    Is there an official .bin or .c export format that is guaranteed to be I²C-host loadable, with APP jump entry?

    No.  Nothing official.  The GUI exports the files in the correct format.

    Is PBMs required, or is EEPROM-style I²C load from 0x00 sufficient in SafeMode?

    PBMs is required.

    What exactly does CMD1 = 0x04 indicate during PBMs?

    This is not clear.  It is most likely only the first byte was read which indicates the size.

    After writing the "PBMc" command the CMD register is read until it is cleared.  This is followed by a read of the data to confirm it is cleared followed by a read of the mode to confirm it is in APP mode.

    Can you provide a minimal .bin or .c patch bundle for SafeMode testing that is verified to reach Boot Flags = 0x07 via I²C?

    What is the meaning of Boot Flags = 0x07?  In the TRM these bits refer to the dead battery flag, a reserved field, and a patch header error.

    https://www.ti.com/lit/ug/slvucr8a/slvucr8a.pdf#page=35

    Regards,

    Chris