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TPS62050 gets damaged in our Circuit

Other Parts Discussed in Thread: TPS62050, TPS62056, TPS62160

Hello

in an earlier revision we were using the TPS62056 (3.3V fixed output). Now we switched to the version with adjustable output TPS62050. We are using the switch converter with a external resistor divider. Using a FET driven by a micro controller one of the resistor values can be changed. So we are able to get 2.7 or 3.3V depending on the FET's state. (see schematics at the end)

The older revision did its work very fine.

The new boards with the configurable voltage appears to work fine as well - but we are getting big trouble: 

The observations are:

  • the output voltage often drops out
  • and the TPS62050 gets very hot
  • the circuit draws a lot of current without any load drawing it
  • replacement of the TPS62050 on these boards with a new chip fixes the problem
  • up to 20% of the boards have the problem just at the first power on after coming from production
  • some of the boards are coming back from the field with the same problem after some time

So the question is: What is wrong with our boards. What did change to the first version what damages the chips? Ideas we have at the moment:

  • the chips got damaged through production (soldering, moisture in package etc.)
  • our idea to switch the resistor divider for getting 2 different output voltages is resulting in not allowed conditions to the TPS62050
  • the standard circuit (Datasheet page 15, Cff) uses a capacitor Cff with about 6.8pF we don't have in our schematic

Does anybody have any idea whats going wrong with our boards?

Schematics

Old fixed voltage version 


New dual voltage version  (2.7 or 3.3V)

 

standard circuit (Datasheet page 15, Cff)

 

 

 

 

 

  • It sounds like the IC is being damaged.  Layout is the most likely cause of IC damage that I see.  Could you send photos of the old and new board layouts?

    What is your input voltage and how is it applied to the Vin pin?

    Your circuit to adjust the output voltage with a FET is fine.  But those 3 resistors and the FET need to be very close to the IC so that the FB pin is not routed all over the board where it can pick up noise.

    Just to let you know, we recently released a much improved version of these older ICs.  Specifically, the TPS62160 would fit your power needs.  I would highly recommend using these newer parts as they support a much smaller solution size and are easier to design with.

  • Hello Chris,

    thanks for your fast response!

    Are you serious that a bad layout will cause IC damage? What are the processes that are resulting in permanent damage?

    To your questions:

    The power source are 4x1.5V AAA Alkaline batteries. We will add the requested pictures of the Layouts next Monday.

    Have a nice weekend.

  • With modern high frequency switching converters, extra parasitic inductance in the layout can cause voltage overshoots that exceed the device's absolute maximum ratings.  This damages the silicon inside the IC which is rated to a certain voltage.

    You need to follow the layout recommendations in the datasheet.  Copying the evaluation module's layout is an excellent way to mitigate layout risk.

  • Hello Chris

    At the end of this post you will find the requested pictures of the PCB layouts.

    We found out that the TPS62050 can be disabled and the supply current reduced to a few uA.

    Furthermore the circuit can be supplied direct by connecting 3.3VDC to the VCC signal instead of suppling it by the TPS62050. Usually this will not cause a higher input current. But connection 3.3VDC to the output of a damaged TP62050 will cause more or less the same input current as when it is supplied through the TPS62050 by itself.

    We also tried to insert a 6.8pF Cff parallel to R19 and remove R21 without any affect to the input current.

    From this it follows that the ouput driver of the TPS62050 could be damaged.

     

    How high is the probability that the IC will not be damaged in a future layout when we change following details of the actual PCB version?

    • Insert a 6.8pF Cff capacitor parallel to R19 (like in the standard circuit)
    • reroute the JTAG TMS signal that it is not close to the supply anymore (see description below the first picture)
    • place a single MOSFet next to R21 to reduce the length of the wire from R21 to Q2

     

    Thank you very much for your answer

     

    new version with TPS62050 (dual voltage) 

    The net routed between the two pads of R19 is a JTAG TMS signal, which is typically just used for programming the device.

    old version with TPS62056 (fixed voltage)

     

  • Your layout looks pretty good, except for the trace between the FB resistor and FET as you noted.  Here are some improvements:

    • Make solid pours between C37 and pins 1 and 10.  It looks like you have tiny trace connecting this cap which creates extra inductance and this stress on the device.
    • Move R20 down to the right of the IC, where it can be next to pins 3 and 5 and route directly to those pins.  This changes the return of that resistor to the GND pin (pin 3) and not the output cap.
    • Move R19 and R21 down also to minimize the length of the FB pin net.
    • Make the distance between Q2 and R21 as small as possible.

    To see if it is the layout of that FET and resistor that is causing your circuit to fail, you could simply remove R21 and see if that IC still fails.

    You should also check that during production and test, no voltages in excess of the absolute maximum ratings are being supplied.  What is your Vin to the device and how is it applied normally and in test?

     

  • Hi Chris,

    how about ESD protection? The DC/DC converter is powered by 4xAAA batteries. The user could potentially touch the contacts of the battery holder and apply an ESD pulse. Is there a best practice for ESD protection of the TPS6250's inputs?

  • Per this post, all of our ICs have ESD protection built in: http://e2e.ti.com/support/power_management/non-isolated_dcdc/f/196/t/100380.aspx You will need to determine if these ratings are sufficient for your application.

    Something else to try would be taking a 'bad' IC that displays poor behavior and putting it on a known good board (such as the EVM).  If the IC acts the same way, then it is the IC that is getting damaged and not something in your external components or test setup that is causing the issue.

     

  • We can definitely say that the TPS62050 is damaged.

    The measured ohm resistive load between the SW and PGND pin is too low, as you can see in the following sorted list:

    8.3E, 30E, 34E, 38E, 39E, 46E, 50E, 62E, 64E, 73E

    The measurements have been done after desoldering the TPS62050.

    Do you know any reason for these damaged output drivers?

  • Yes, it seems the IC is damaged.  This is usually a result of exceeding some absolute maximum rating of the device.  Could you check if any of these likely causes apply to your design?:

    • Vin exceeds absolute maximum rating due to hot plug or test setup.  Could you measure the Vin on the board when the batteries are inserted?  How is Vin applied during test?  Could you measure this?
    • Excessive reverse current overheats device when Vout is externally supplied.  You mentioned that 3.3V is applied to the output for programming.  This voltage will travel through the high side FET's body diode to the input bus.  If there is any load or a short on the input bus, this current will be excessive.  It is not limited.  Can you measure the current going into the IC when you are applying the external 3.3V?  To do this, you can remove the TPS62050 and measure the current from your 3.3V supply.  Then, reinstall a new IC and measure the current.  The difference is what goes into the IC.
    • Noise getting into the FB pin.  Have you tried removing R21 and installing a brand new IC?  Removing R21 will not fix a damaged IC, but could prevent damage to a new IC if it is indeed the cause of the damage.

    Some possible solutions that might help would be:

    • Adding more input capacitance.  Ideas are a smaller one (10uF or so) near the IC as well as a bulk electrolytic or tantalum by the battery connector.
    • Add a diode in series with the input supply to the IC to eliminate reverse current from Vout to Vin.  The 47uFinput cap would go between the diode and IC.  The diode would just supply the IC and no other circuitry on the board.
  • What do you mean with hot plug? Hot plugging the supply or the load?

    The device is potential-free and the supply is as already mentioned a battery-package with at most 6.6VDC. Unfortunately there is actually no production test.

    There is a reverse and battery protection between the battery plug and the TPS62050 (Q1 and Q9):

    Due to that fact reverse current should not be the problem. However I've measured it as you told me and there is no problem with reverse current.

    Unfortunately we couldn't reproduce the damage of any further TPS62050 and so not  verify any of your recommended improvements. As you can see in the new schematic we have inserted the 6.8pF cap in the FB path and also planed to use TVS diodes as an ESD protection. An additional 100nF cap (C23) should handle high frequency signals on the voltage input. Your recommended diode in series is already included in our advanced reverse protection (diode in Q1).

    I have redesigned the PCB as you suggested (expect the position of the resistors, because the hatched area on the right-hand side is a keepout for placement).

    Can you find any other detail to fix?

  • An additional question because you mentioned hot plugging:

    Has the TPS62050 any problems with high dynamic loads? We are using it to supply an ultra low power device which has very dynamic power requirements.

    During the most of the time it only needs a few dozen uA. But there are also actions which load the TPS62050 within a few ms with almost 500mA .

    But this will not be the reason for the mentioned problem because there are damaged devices which haven't had anytime firmware loaded on it and so not loaded the TPS62050 with these dynamic loads.

  • The new layout looks good.

    This IC can handle load transients.  This is shown in figure 14 in the datasheet.  It is always a good idea to make sure the circuit is stable when subjected to a load step.  This app note describes one way: http://www.ti.com/lit/an/slva381a/slva381a.pdf

    By hot plugging, I did mean on the input.  This is a common cause of overstress.