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TPS65219: Substantial power leakage in production variant of TPS6521903

Michael Williamson
Expert 1985 points
Part Number: TPS65219

Tool/software:

We have an AM62x design that is using the TPS6521903.

During initial device testing, we had used a pre-production GP processor and a pre-production PMIC, PTPS6521903, to measure power consumption while the processor was in sleep mode (rtc -wake 30 -m mem).

In that test, we observed 12 mA @ 3.3V (40 mW) entering the PMIC, and on the exit rails we observed roughly 27 mW of total power consumed.  The 13 mW was attributed to the PMIC and a couple of pullup resistors around the PMIC control lines.

We have since repeated this test with production silicon HS/FS devices and a production TPS6521903 device.  

We are now measuring 60 mA @ 3.3V (200 mW) entering the PMIC, but on the exit rails we are still observing approximately the same 27 mW of power consumed.

We have gone so far as to take hardware using the production device and swapping only the TPS6521903 with some remaining pre-production devices PTPS6521903 we had in stock and we see the input current drop from 60 mA back to the 12 mA we had originally measured.  No changes to the software or any other circuitry.

Did something change between the pre-production and production PMIC devices?  

This is a critical issue, as it implies we cannot use this solution for certain battery power applications.

We note that the AM62x EVM does not provide a way to measure the PMIC input current, and the current from the USB-C input while the processor is asleep corresponds to 720 mW, though there is a lot of other circuitry still powered on the EVM.

We have ordered a TPS65219 EVM to try to reproduce the issue there, but it's not clear if that EVM corresponds to the same firmware version or how to replicate that setup yet.

Any insight would be appreciated.  I am attaching a figure of the power measurements we have made while the processor is in sleep mode. They seem fairly consistent with the TI AM62x power consumption report.

Thanks,

Mike

/resized-image/__size/320x240/__key/communityserver-discussions-components-files/196/PTR6521903_5F00_PowerIncrease.png

  • 0
    TI__Expert 6245 points

    Hi Michael,

    Thank you for reaching out on e2e.

    Is it possible to do the register dump of TPS65219 so that we can see if there is any change in the settings between the 2 samples?

    The attached picture is not clear. Can you please send a clear picture.

    So, other than swapping the TPS6521903 with a 'P' marking device, there is no other setup or test method changed between the two?

    Sathish

  • 0 in reply to Sathish Vallamkonda
    Expert 1985 points

    Hi Sathish,

    Do you have a recommended way to dump out the registers for the TPS65219?  We are booting to linux, so we would need to either run something in uBoot or disable the PMIC driver in the kernel, correct?  We will be happy to collect the data you request.

    I am trying to upload the PNG file, which is clear on my end.  Not sure if it will work.

    Yes, all we did was swap the TPS6521903 with PTPS6521903.

    With regards,

    Mike

  • 0 in reply to Michael Williamson
    TI__Expert 6245 points

    Hi Michael,

    I am not sure about the linux environment but just need to read the registers from 0x00 to 0x53.

    Do you see any difference in the output rails between the two versions? or any settings changed in 'P' device during development?

    Sathish

  • 0 in reply to Sathish Vallamkonda
    Prodigy 70 points

    Hi Sathish,

    We went ahead and just forced reads of the whole address space from Linux; we did leave the PMIC driver enabled, but that didn't seem to cause any issues.

    Aside from a couple revision fields, the only difference in the documented registers (only up to 0x41 in the datasheet) is the MODE_STBY_CONFIG field, which is 1 (STBY only) in the PTPS device and 2 (MODE and STBY) in the TPS device.

    This seems like the culprit: the MODE/STBY pin is always high, so our understanding is the buck converters will always be in forced PWM mode. With the TPS device, we do see that one of the bucks is always switching around the nominal 2.3 MHz even when the AM62 is asleep, while with the PTPS device, the same buck drops to around 40-50 kHz when we put the AM62 to sleep; and if we change only MODE_STBY_CONFIG (to 1) in the TPS device, we observe the same lower input power as with the PTPS device. (We haven't yet scoped the other two bucks.)

    We have a few follow-up questions:

    1. In a production setting, is it safe to change the MODE_STBY_CONFIG field while the output rails are enabled? We didn't see a note not to do this in the datasheet, but some other settings had warnings about this, so we wanted to confirm.
    2. Are there any downsides to setting MODE_STBY_CONFIG to STBY only? We notice that all of the preconfigured NVM variants have it set to MODE and STBY.
    3. We've connected the MODE/STBY pin to the AM62's PMIC_LPM_EN0 pin as shown in "Powering the AM62 with the TPS65219 PMIC", (with an additional 4.7k pull-up), but as mentioned above, the pin stays high even in sleep. We need to double check our pinmuxing here, but should the AM62 be driving/pulling PMIC_LPM_EN0 low when it enters sleep? Is that configurable somewhere?

    In case they show anything else relevant, here are the full register dumps as well:

    PTPS:

         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 00 03 7f 0b a6 98 05 76 98 a4 86 22 22 50 22 30    .??????v???""P"0
10: 22 42 80 60 02 60 c9 5d c0 00 cc 00 00 00 07 41    "B?`?`?]?.?...?A
20: dd 7f 02 00 00 60 30 00 00 10 7f 00 00 00 00 00    ???..`0..??.....
30: 00 00 00 04 00 99 00 00 00 00 00 00 00 00 00 00    ...?.?..........
40: 03 20 cd 01 01 00 4e 3b 00 78 15 15 14 0c 0e 3e    ? ???.N;.x?????>
50: 46 00 00 17 03 00 90 16 24 80 0e 37 63 6f 66 1b    F..??.??$??7cof?
60: 10 22 1b 24 a0 0d 37 74 6f 69 1a 0f 22 1a 24 60    ?"?$??7toi??"?$`
70: 04 37 63 6f 62 19 09 1e 19 e4 e4 e4 24 24 24 e4    ?7cob???????$$$?
80: e4 e4 0f d6 84 13 1c 26 94 14 20 1c 66 23 1c 1f    ???????&?? ?f#??
90: 09 1f 1e 1f 09 21 00 00 00 00 00 00 00 00 00 00    ?????!..........
a0: 00 21 09 00 00 00 00 00 00 00 00 00 00 00 00 00    .!?.............
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 08 00 00 08 00 00 00 3e 87 3e 00    .....?..?...>?>.
d0: 00 03 7f 0b 00 1f 00 1e 56 1e 52 56 52 30 56 30    .???.?.?V?RVR0V0
e0: 18 04 24 24 05 04 11 11 18 2e 34 2e ec 07 07 00    ??$$?????.4.???.
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

    TPS:

         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 00 03 7f 0b a6 98 05 76 98 a4 86 22 22 50 22 30    .??????v???""P"0
10: 22 42 80 60 02 60 c9 5d c0 00 cc 00 00 00 07 41    "B?`?`?]?.?...?A
20: de 7f 02 00 00 60 30 00 02 10 7f 00 00 00 00 00    ???..`0.???.....
30: 00 00 00 04 00 99 00 00 00 00 00 00 00 00 00 00    ...?.?..........
40: 03 40 14 1d 02 31 eb 2d 01 78 15 15 15 0d 0e 3e    ?@???1?-?x?????>
50: 47 00 00 17 03 00 90 0b 24 80 2a 36 63 44 6f 21    G..??.??$?*6cDo!
60: 28 27 20 24 a0 22 36 63 54 68 20 1e 24 20 24 80    (' $?"6cTh ?$ $?
70: 1b 36 63 78 69 20 1c 24 20 e4 e4 e4 24 24 24 e4    ?6cxi ?$ ???$$$?
80: e4 e4 0f d6 63 0e 21 24 85 0e 24 1c 67 1c 21 20    ????c?!$??$?g?!
90: 08 25 24 1f 09 20 00 00 00 00 00 00 00 00 00 00    ?%$?? ..........
a0: 00 20 09 00 00 00 00 00 00 00 00 00 00 00 00 00    . ?.............
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 08 00 00 08 00 00 00 3e 87 3e 00    .....?..?...>?>.
d0: 00 03 7f 0b 00 1f 00 1e 56 1e 52 56 52 30 56 30    .???.?.?V?RVR0V0
e0: 18 04 24 24 05 04 11 11 18 2e 34 2e ec 07 07 00    ??$$?????.4.???.
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

    Thanks,
    Zach

  • 0 in reply to Zach Miller
    TI__Expert 6245 points

    Hi Zach,

    Thanks for the NVM settings.

    As you can see in register 0x41, the NVM revision is different between the PTPS and TPS devices. And you found the difference in STBY settings.

    Let me review your questions and will get back to you.

    Sathish

  • 0 in reply to Sathish Vallamkonda
    TI__Expert 6245 points

    Hi Zach,

    1. It is safe to change MODE_STBY_CONFIG when the rails are enabled, but pay caution to the result of the change. Only the polarity shouldn't be changed after power up.

    2. It is okay to configure as STBY only, but the reason i would assume for setting it to MODE and STBY is so that when it enters STBY mode it will force the converters from forced PWM mode to auto PFM mode.

    3. Since the MODE_STBY_POLARITY is set to '0', i would assume PMIC_LPM_EN0 would go low on enabling low power mode. Can you please check with AM62 team on why it is not so?

    Sathish

  • 0 in reply to Sathish Vallamkonda
    Expert 1985 points

    Hi Satihsh,

    For 3:

    We have posted a second E2E on the processors forum about the PMIC_LPM_EN0.  There isn't much documented about this pin in the TRM or the datasheet for the AM62x family of processors.  Link to E2E post below.

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1508052/am625-pmic_lpm_en0-is-not-toggling-when-entering-sleep-mode

    Thanks,

    Mike

  • 0 in reply to Michael Williamson
    TI__Expert 6245 points

    Hi Mike,

    thanks, let's wait for the response. Low power modes are handled by MCU.

    Sathish