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UCC28070A: Using ACS756 with UCC28070 Current Loop – Stability Concerns?

Ki-Young Kim
Prodigy 10 points
Part Number: UCC28070A
Other Parts Discussed in Thread: UCC28070

Tool/software:

Hi TI team,

I'm designing a 6.6kW interleaved CCM Boost PFC using UCC28070APWR.
I’m using Allegro’s Hall-effect current sensor ACS756 to feeding its output (via resistor divider and LPF) into CSA and CSB pins for the current loop.

The setup is as follows:
- ACS756 has a 2.5V reference and 40mV/A sensitivity.
- For ±50A range → output spans 0.5V ~ 4.5V.
- I use a resistor divider (10k:20k) to scale the 4.5V max down to 3V max at CSA/CSB.
- There's also a 1k + (1uF, 0.1uF, 6.8nF) to suppress switching noise before reaching CSA.

Now, I understand that TI usually recommends using current sense resistors or CTs instead of Hall sensors due to potential bandwidth or stability concerns in analog loops.

But I would like to confirm:
1. Is there any known issue with using ACS756 (with proper filtering & scaling) in the current loop of UCC28070?
2. What loop stability considerations should I be aware of?
3. Do you recommend adjusting the PKLMT voltage if I'm using 3V as CSA/CSB peak?

I’m attaching a schematic snippet for reference (see below). Please let me know if this approach is acceptable or risky in any specific way.

Thanks in advance.

------------------------
Ki Young

  • 0
    TI__Mastermind 40340 points

    Hello Ki, 

    I have no experience with the ACS756 Hall-effect sensor, however, after scanning through its datasheet I have the following concerns and observations: 

    1.  It's bandwidth is limited to ~120kHz, so it will not reproduce the switch current cleanly for narrow duty cycles.  Also, it has a ~1us propagation delay and ~3us rise time which will affect narrow pulses significantly.  At best, this can lead to higher distortion at high-line peaks.  At worst, it may prevent detection of excessive peak currents until they become destructive, depending on certain fault conditions.    

    2.  The 0.5V output offset at 0A will probably introduce significant dead time at the AC-line zero-crossing, making THDi even worse.  IF you can level-shift most of this out, it would be helpful.

    3.  In control systems, time delays introduce a lagging loop phase shift (closer toward 180 degrees) so loop stability can be significantly affected unless phase lead can be obtained to counteract it.   Excessive R-C filter time constants introduce additional signal delays which make this problem worse.  Minimize R-C filtering to only what is absolutely necessary.  

    4.  I do recommend adjusting PKLMT to match the actual peak signal at which you want the limiting to apply.  PKLMT is not a fixed level.  It is intended to be varied as needed in each design according to the peak current where limiting is expected. 

    I am not saying that this Hall-effect sensor scheme cannot be made to work.  I am saying that there are limitations to this particular sensing device that must be accepted or compensated to achieve reasonable PFC performance. 

    Regards,
    Ulrich