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TPS65070: External resistor divider?

Anonymous
Anonymous
Guru 17045 points
Other Parts Discussed in Thread: TPS65070

Hi,

I would like to ask a question with TPS65070.

Question 1

 

In register description of DEFDCDC1, DEFDCDC2_HIGH and DEFDCDC3_HIGH at page 55, bit 7 are all extadj. When this bit is enabled, an "external resistor divider" is needed.

This is also supported by Electrical Characteristics in page 5-6, in which we see when using "internal resistor divider", VOUT range [0.725, 3.3], as shown in page 57; when using "external resistor divider", the output range is [0.6, VIN].

However, through the document I didn't find any example showing how "external resistor divider" is connected, nor does any diagram even contain a drawing of the "internal resistor divider".

Could anyone explain on how do external and internal resistor divider work? How they are connected? Could anyone show a diagram of them?

Question 2

I also noted that DEFDCDC2_HIGH and DEFDCDC3_HIGH has [bit 7, extadj], but there _LOW counterpart DEFDCDC2_LOW and DEFDCDC3_LOW do not. Does it mean when DEFDCDC3/2 pin is pulled low so that corresponding _LOW resisters are used, there is no way to use external resistor divider?

 

Zheng

  • 0
    TI__Genius 17240 points

     

    You connect the resistor divider between the output of the inductor, the VDCDC1 pin and ground just as you would with most adjustable switch mode buck converters.

    If you set DEFDCDC3_HIGH[7]=1, the register DEFDCDC3_LOW is ignored. 

     

  • Anonymous
    0 Anonymous in reply to Daniel Acevedo
    Guru 17045 points

    Daniel,

    I think this question is resolved. Thanks.

    But how does a voltage divider using external resistor scale 0.725V to 0.6V? If there are R1 and R2, with R1 connected to L1 output and R2 to ground, and VDCDC1 to junction of R1 and R2, then the ratio between R1 and R2 is arbitrary.

    For example, if R1:R2 = 1:9, then VDCDC1 senses only 1/10 of L1 voltage. And if this 1/10 value is internally compared with [0.725, 3.3], then actual L1 would be between [7.25, 33]. There is of course upper limit of the device capability which I didn't consider here. I just wonder how the scaling from 0.725→ 0.6 goes.

     

    Zheng