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TPS568215: Clarification on Output Capacitance Limits for TPS568215 in Zynq UltraScale+ Designs

Hamed Sotoudi Namin
Prodigy 10 points
Part Number: TPS568215
Other Parts Discussed in Thread: TIDA-01480

Tool/software:

Dear TI Support Team,

I am currently working on a design using the TPS568215 for powering the Zynq UltraScale+ FPGA (model 5EV), and I have encountered some confusion regarding the output capacitance limitations and the recommended capacitor values.

The TPS568215 datasheet (page 20, Table 5) specifies a maximum output capacitance of 500 µF. However, the power requirements outlined in UG583 (Xilinx documentation) for the Zynq UltraScale+ indicate a need for 330 µF, 4 x 100 µF, 47 µF, and 10 µF capacitors for the VCCINT and VCCINT_IO power rails. These values seem to exceed the 500 µF limit specified in the TPS568215 datasheet.

Could you please clarify whether the 500 µF limitation refers only to the capacitors directly connected to the output of the TPS568215, or if capacitors can be distributed across multiple power domains of the FPGA? Additionally, how can we ensure compliance with the output capacitance limit while meeting the power requirements for the Zynq UltraScale+?

(this chip is recommended in your desig TI Designs: TIDA-01480)

Thank you for your time and assistance. I look forward to your guidance on this matter.

many regards,

Hamed Sotoudi

  • 0
    TI__Mastermind 26800 points

    Hi Hamed,

    You are correct in that the direct output capacitance at the output has to be limited to 500uF or less and this is a function of the stability requirement for the TPS568215. However, you can add additional capacitance at the load as required. This will typically work since there will be trace resistance from the output of TPS568215 to the load which will add enough damping on the output filter and not affect stability of the TPS568215. Hope this helps. 

    Thanks,

    Amod

  • 0 in reply to Amod Vaze
    Prodigy 10 points

    Dear Amod,

    thanks for your instant reply! for such high current output ( rating from min 4A and max 10A ) and output 0.85 V wih 3% tolerance we need a low resistance power plane and path, that means we put a power plane and the converter is connected to the plane directly via several big vias. Unless you mean the vias itself is enough for damping!

    regards,

    Hamed

  • 0 in reply to Hamed Sotoudi Namin
    TI__Mastermind 26800 points

    Hi Hamed,

    Yep, if there is not enough damping resistance, there is possibility of instability to occur. Cannot tell if vias themselves will create enough separation or not. It may not be precisely the same layout but you can possibly try the same cap distribution on an EVM and see if it holds well during load transients for example to check if the design is stable. 

    Thanks,

    Amod