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Power Good (PG) output remains low, even though VDD is active

Part Number: TPS23734

Tool/software:

Hi Team,
We're using the TPS2373-4RGW Poe PD controller in our design. The hardware has been assembled and is currently under testing. 
 
We've noticed an intermittent issue in some units: the Power Good (PG) output remains low, even though VDD is active — indicating that PoE negotiation has completed successfully and the internal hotswap MOSFET has turned on. This behaviour is inconsistent, showing up roughly once in every 10 power cycles (Hot plugging the LAN cable). We're using the POE300 1.0 as the PSE during testing. 
 
Attaching the image of the design section of TPS2373-4RGW.
 
Design Section
 
The block diagram of the power section.

Block Diagram of the power section

Observation:
  • Probing Points Positive probe Negative probe Expected Voltage Measured Voltage
    VCC_48V0_PRIM TP26 TP55 53-57VDC 53.65V
    VC_IN_12V0 TP237 TP55 ~12V 12.09V
    PD controller PG_48V0 TP36 TP55 ~9V 0.3V
Please let us know what could be the potential cause of these events.
  • Hi LENIN,

    Thanks for reaching out 

    Two things could be related:

    1. VC_OUT needs to be 10x higher than VC_IN. Also recommend to have 100k instead of 10.5k resistor for less power loss on this resistor

    2. The C1 between VDD-RTN normally needs to be 10x - 20x times larger than the C2. So when the back-back breaker turning on C1 can help to charge the C2 without too much voltage drop on C1. 

    Otherwise, charging C2 may cause too high inrush and TPS2373-4 foldback.

    Best regards,

    Diang