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TPS7H4104-SEP: Multi-phase Output Configuration and Multi-device Synchronization

Alex Driskell
Prodigy 60 points
Part Number: TPS7H4104-SEP

Tool/software:

The datasheet does not provide much guidance on how to use this part (or multiple parts) to power a single power supply rail with multiple buck converter channels.

Is there a recommended way to tie the sense, compensation, enable, power good and other pins for this type of configuration? The soft start and tracking pin is covered in the datasheet, so it seems clear those should be tied together for simultaneous startup. The EN_SEQ pin should also be left open to disable the sequencing feature. The rest isn't clear from the datasheet.

Also, if a pair of TPS7H4104-SEP devices are used for a single power rail, say channels 2 & 4 on one device and 1 & 3 on the other are used, would the phasing be guaranteed to be 90 degrees between all 4 channels assuming the same signal drives the sync pin on both devices?

  • 0
    TI__Expert 5181 points

    Hi Alex,

    The TPS7H4104-SEP is still in "preview" status currently, so more detail may be added to the datasheet from now until full release.

    To parallel channels on the TPS7H4104-SEP, SS, EN, COMP, VSNS, and VOUT should be tied together. PG can also be tied together for a single PG signal. The EVM for this device, TPS7H4104EVM, provides connections to parallel CH1 with CH4, and CH2 with CH3. Connections made between the channels are shown with DNP marked 0Ohm resistors. Similarly, all four channels could be connected in parallel, although the EVM was not designed to support that mode.

    When connected in parallel, some component calculations may need to be changed. In some of our other buck devices, these include the the SS capacitor and COMP components. Section 9.2.4 "Parallel Operation Compensation" in the TPS7H4011-SP datasheet contains useful guidance on COMP component calculation modifications needed for parallel systems with both a single compensations network, and placing individual compensation components at each device while leaving the COMP pins connected.

    If more than one device is being supplied with the same SYNC signal, then each phase of the two device would be in sync with each other (e.g. CH1 on device 1 is in phase with CH1 on device 2, CH2 on device 1 is in phase with CH2 on device 2, etc...) That would mean that channels 2 and 4 on one device, and channels 1 and 3 on another device would all be 90 degrees out of phase with each other just as if it were a single device. The exception to this being the device-to-device variation of the SYNC to SW delay specification (tSYNC_DLY  in the datasheet Electrical Characteristics table). Variation in this specification will cause the timing between the two devices to be less consistent than a single device, but the variation from Typ to Max is relatively small so shifting due to this specification would likely be of little impact.

    Thanks,

    Andy