This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS65987DDJ: TPS65987DDH OCP issue

Part Number: TPS65987DDJ
Other Parts Discussed in Thread: TPS65981,

Tool/software:

Hi TIer

My customer use GUI TPS65981_2_6_7_8 Application Customization 6.1.4 to configure the TPS65987DDH.

When configuring SINK, Customer set the overcurrent protection point to a maximum of 3A, but the actual test found that the PD adapter protection did not shut down the PP channel.
When configuring SOURCE, customer set the external maximum output current to 0.9A, CC pull down 5.1KΩ test and found that the actual test was still us the DCDC 3A overcurrent protection, The PP channel is also not closed.

So could you help to provide some test methods or possible reasons why the OCP settings do not work, whether in source or sink mode.

Thank you very much.

  • Hi Tony,

    A couple comments before we begin, please make sure the customer understands:

    1. TPS65987DH, DJ, and DK are NRND and should not be used for new designs
    2. You mentioned the TPS65987DDJ in your title thread, but seem to be interested in the TPS65987DH. Know that the TPS65987DDJ is meant for only TBT designs following specific intel reference designs.

    Please share the PJT the customer is using.

    Please confirm that they are using the TPS65987DDH.

    When configuring SINK, Customer set the overcurrent protection point to a maximum of 3A, but the actual test found that the PD adapter protection did not shut down the PP channel.

    How did they test the sink? Did they just ramp an E-load? What is being used as the source?

    When configuring SOURCE, customer set the external maximum output current to 0.9A, CC pull down 5.1KΩ test and found that the actual test was still us the DCDC 3A overcurrent protection, The PP channel is also not closed.

    What do you mean here? That they expected the PTS65987 current protection to kick in around .9-A but instead, the DC-DC sourcing the power limited it at 3-A?

    Can you also share a block diagram of how they are testing so I can better understand their methods?

    Thanks and Regards,

    Chris

  • Hi Christopher

    This subject is DDJ because I can't ask a question about DDH on E2E, it can't search anymore.

    I make sure they use TPS65987DDH. And I already told them we not suggest TPS65987DDH in new design.

    But The customer has just finished designing so they will replace the chip on the next generation. 

    Did you mean that the load should be increased step by step? I think the customer may be a jump load for an instant, would that make a difference?

    I think we will solve the source problem first.

  • Hi Tony,

    This subject is DDJ because I can't ask a question about DDH on E2E, it can't search anymore.

    I make sure they use TPS65987DDH. And I already told them we not suggest TPS65987DDH in new design.

    Ok

    Did you mean that the load should be increased step by step? I think the customer may be a jump load for an instant, would that make a difference?

    I just want to understand how they are testing. Please confirm their setup and provide a block diagram so I can better understand how they are testing and potentially try it on an EVM.

    I think we will solve the source problem first.

    Please share the pjt file they are using. This is a configuration file used with the GUI to configure the PD controller. I can't debug without this information.

    Please share more information on how they are testing. Are they using a non-pd sink? How are they drawing the current? From VBUS with and E-load?

    Thanks and Regards,

    Chris