Tool/software:
Hi,
I have a question regarding the routing of the VEEA node (pin 35) relative to the general VEE plane.
Under Section 12.5.1 in the datasheet (page 46), it is recommended that "VEEA (pin 35) should be isolated through all PCB layers, from the VEE plane as shown in the red box below."
Does this mean that we should avoid any connection between VEEA and the VEE plane on the PCB? This would mean that there is no single point conenction between VEE and VEEA on the PCB (external to the IC)?
Is this because VEEA is internally connected to VEE within the IC?
We are a bit confused by the conflicting recommendation in this section and the pin configuration table. Could you please provide any advice or tips on managing this aspect of the design?