LM25085: PSPICE model of LM25085 has an error in RT pin

Hi Haider,

Please share the schematic, simulation file and clarify the following points before I check with the modelling team to debug the simulation issue.

• Which voltage you are measuring as 1.16V? 
• What is the output voltage?

Regarding the operation of ON timer:

When the FB pin voltage falls below the feedback reference, Q1 is switched on for a time period determined by the input voltage and a programming resistor (RT). Following the on-time Q1 remains off until the FB voltage falls below the reference. Q1 is then switched on for another on-time period.

The on time of the PFET gate drive output (PGATE pin) is determined by the resistor (RT) and the input voltage (VIN) and is calculated from Eq3 data sheet.

Regards 

Arpita

Arpita

in the simulation, measure the voltage at the chip pin2 (RT) is always 1.16V regardless of the RT resistor connected.

output voltage is 26V, VIN is 36

the Ton time @243K resistor should be 1.07uSec according to the equation, 

I noticed when I don’t use ripple insertion (one of the three techniques shown in the data sheet) the on time gets up to 9uSec, when I use any of the ripple insertion the time goes back to 1.1uSec. It might have something to do with the stability of the design 

I will attach the simulation file.

in all cases, with ripple or without, the voltage @RT is always 1.16v

in the real circuit I constructed, the measured voltages follow exactly the data sheet as well as the timing, but noticed when I use ripple insertion the switching becomes more stable, that’s understood as this is a COT topology, and needs ripple in phase with the inductor current on the FB pin to properly switch.

cheers

haider

Hi Haider

• The ON-time issue is now resolved in simulation after using proper ripple injection circuit.

              It is required to insert proper values of ripple injection network components [Excel tool https://www.ti.com/tool/LM25085-5085QUICK-CALC

is useful guide for this] for stable and reliable operation of the IC.

• Please attach the simulation file for further debugging of simulation error in RT pin voltage.

Hi 

yes it’s resolved, I use the same excel calculator you advised.

the simulation model is the one on the TI website of the LM25085, I did not change any thing in it, you can download it from the LM25085 page, unzip it and run it, measure the voltage on the RT pin, change the resistor value to any other value, you will notice it will not change.

also I noticed today on my PCB, which I installed a 243.1K resistor as RT, the on time in one cycle is correct and in the cycle after it it stretches a bit to 1.3uSec, the regulator is in CCM mode, the layout is optimum, I do have quite large spike at the switching edges, but the FB signal swings from 1.2-1.31V, the switching on the FB threshold is correct around 1.25V, the mosfet total delay is 36 nSec, the current sense is not triggered, I have a good margin of about 60mV out of 167mV trip voltage.

what can cause that? Is it due to inductor and capacitor feedback control loop? The inductor is 33uH, output capacitor is 2X10uF, ripple resistor 100mOhm, Cff 2nF for the ripple injection, voltage divider for feedback is 39K top and 1.87K bottom.

input capacitor 2X10uF XR7 , VIN fixed at 36V from a lab power supply, output current using electronic load of CC 1.5A , output ripple is about 60mV , output voltage correct at 27.3V 

does the on time change or should be absolutely fixed?

I don’t know how to attach the Altium designer file in this web chat!

what could be the cause of changing on time?

Hi again,

just thought of might cause this issue, is it possible that my output capacitors are higher than the required, that is causing a slight phase shift between the inductor current and the feedback signal?

the calculator recommended 5uF, on the 33uH and the 638KHz switching frequency, I installed 20uF, can that cause the pole to shift?

As I have said, 

When the FB pin voltage falls below the feedback reference, Q1 is switched on for a time period determined by the input voltage and a programming resistor (RT). Following the on-time Q1 remains off until the FB voltage falls below the reference. Q1 is then switched on for another on-time period.The on time of the PFET gate drive output (PGATE pin) is determined by the resistor (RT) and the input voltage (VIN) and is calculated from Eq3 data

for better understanding of your issue, kindly share the following.

• Please provide complete schematic and filled in excel tool for review and further debug.
• Please provide waveforms of SW node (where you mention about spikes), FB, Vout 
• What is output current?

Note that this device is based on Constant on Time architecture, and there is no loop compensation and all.

Regards

Arpita

Regarding the simulation issue, I will try to run the model and get back to you within couple of days.

Meanwhile please get back to us for the above issue.