LM5122: Inrush current.

Hi Niklas

Thanks for your support.

The client company says that it is difficult to change the IC.
Is there a way to improve the external circuit additionally without changing the IC?

Thanks

Hi David,

If customer confirmed that this inrush is coming just from turning on the power supply, I see no way of optimizing the design without layout change, as this inrush is not related to the controller.
They could stay with LM5122 and implement an external circuit that limits the inrush current during turn-on.
If there is a possibility for their system to slowly ramp up the supply voltage, this would also reduce the inrush current.

Best regards,
Niklas

I’m currently working on a high-current boost converter design using the LM5122, and I noticed that the inductor current in my application exceeds 70 A during startup or load transients.

Upon reviewing the LM5122 EVM design, I observed the following:

• The inductor used on the EVM does not appear to be rated for saturation currents at this level.

• There is no inrush current limiting circuitry (e.g., NTC thermistor, precharge FET, or disconnect switch) implemented.

Could you please clarify:

1. How was the EVM designed to safely handle potential inductor saturation or high inrush current events?

2. Is the EVM intended only for lab-level demonstrations under limited load conditions?

Any recommendations on how to adapt the EVM or production design to support high-current use cases would be greatly appreciated.

One more question:

The inrush current occurs before the IC starts switching, and the inrush path seems to be:
input → inductor → FET body diode → output capacitor.

In this case:

1. Is it appropriate to apply the FET’s body diode ID pulse rating to evaluate the stress from this inrush current?

2. Also, if the inductor exceeds its saturation current rating (approx. 30 A) just once briefly during startup,
   would that be acceptable or could it lead to potential long-term reliability issues?

Hi David,

lee chungwoo said:

The inrush current occurs before the IC starts switching, and the inrush path seems to be:
input → inductor → FET body diode → output capacitor.

You are correct.

There is no protection against this sort of inrush current on the EVM.
Also in the failure case the the output is shorted, there is not protection implemented, as the controller cannot do anything to block this current path.

The risk of damaging the inductor is small.
If an inductor saturation, the inductance reduces until the inductor behaves like a short circuit.
Once the current reduces, the inductor recovers and there are no long-term reliability issues.

The MOSFET would be the weakest part, because it can break if it heats up too much from the current through the body diode.
However, as the inrush only occurs for a very short time period, there is no damage seen in most cases. (This depends on the MOSFET component, but I am not an expert on this field)

Best regards,
Niklas

We are using the CSD18543Q3A MOSFET from TI, and we see that the ID pulse rating is 156A.
Can the body diode also be considered to support the same ID pulse rating, or does it have a different limit?

Hi David,

I checked the datasheet of CSD18543Q3A and did not find any ratings for the body diode.
The body diode should be able to support the continuous current rating of the MOSFET. However, this is rated for 60A.
In the measurement, the current peak goes up to ~80A, so I cannot give a statement here.

I will loop in our MOSFET expert team.
Hopefully they can give you more information about body diode ratings of the MOSFET.

Best regards,
Niklas

Hi David,

Thanks for your interest in TI FETs. In theory, the body diode max current should be the same as the FET when it is on. However, it is limited by power dissipation. How long is the inrush pulse? Can the customer provide a zoomed in waveform showing the detailed inrush pulse? For a single pulse, we can estimate the junction temperature rise using the normalized transient thermal impedance graph in Figure 1 of the datasheet. I'm including a link below that explains how to calculate the maximum body diode current.

https://www.ti.com/lit/pdf/SNVAA86

Best Regards,

John Wallace

TI FET Applications

Hello,

I’ve reviewed the TI application note SNVAA86 – “Power MOSFET Body Diode Continuous Current Carrying Capability” and I understand how to calculate the continuous body diode current using the formula:

ISD = (Tjmax - TX) / (RθJX × VSD)

However, I could not find any explanation or method in the document to evaluate short, high-current pulse events through the body diode — such as inrush current conditions.

I’m currently evaluating the CSD18543Q3A MOSFET, and during system startup, the body diode sees an inrush current of 121A lasting approximately 120µs (single event).

Since SNVAA86 focuses on steady-state dissipation and continuous current, I’m unsure if the following pulse energy method I found online is technically valid for a single-shot inrush condition like mine:

E = I × V × t = 121A × 1.0V × 120µs = 14.52mJ

Then, comparing that to the datasheet’s EAS rating of 55mJ, the stress is about 26% of the maximum.

My questions:

1. Is it correct and acceptable to use this E = IVt formula to evaluate pulse inrush energy through the body diode?

2. Does TI provide any formal guidance or margin recommendations for body diode stress under non-repetitive pulsed inrush conditions?

3. Would you consider 121A for 120µs safe through the body diode of the CSD18543Q3A under datasheet conditions?

I appreciate any clarification or additional references you can provide.
Thank you very much!

Best regards,