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UCC5880-Q1: Questions regarding the startup and shutdown sequence and the behavior of the output terminals of the UCC5880.

Toshihide Tanaka
Prodigy 10 points
Part Number: UCC5880-Q1

Tool/software:

I am developing a gate driver board using the UCC5880.
Currently, I am verifying the operation of the gate driver IC UCC5880, but I am facing an issue where the OUT signal does not appear even when there is no fault output.
I would like to consult about this issue.
Regarding the UCC5880, after performing the terminal processing as specified in the datasheet (such as connecting unnecessary ports to GND), the issue is that the OUT signal is not output when the PWM signal is input.
We are using isolated power supplies of 18V and -4V, and while the OUTL terminal output is correctly pulled down to -4V, the OUTH terminal remains at -4V even when the PWM signal is input.
The behavior is similar to the mode described in the datasheet under the section "6.2.3.3 OUTL Clamping Circuit," where both OUTH and OUTL are fixed to VEE2 (in this case, -4V). This state occurs when 18V is not applied to VCP, but it has been confirmed that 18V is applied to the VCP terminal. Additionally, the nFLT is always in a Hi (no error) state.*
Currently, I suspect that the issue might be related to the startup sequence of the gate driver IC. Is there a specified startup sequence (VCC1, VCC2, VEE2) or a timing chart for the UCC5880?
  • 0
    TI__Mastermind 25980 points

    Hi Tanaka-san,

    The device shouldn't require a specific startup sequence. Could you check if ASC_EN_PRI, ASC_EN_SEC, or any of the GDx pins are being driven high?

    Regards,

    Max Verboncoeur

  • 0 in reply to Max Verboncoeur
    Prodigy 10 points

    Hello Maxwell,

    Thank you for explaining the startup sequence. I understand that there is no specific startup sequence, which leads me to believe that the issue lies with the IC terminal inputs.

    Current Status: We are verifying the initial operation of the gate driver IC with the minimal configuration (testing without SPI communication).

    Therefore, we are testing whether the PWM signal can be output using only GDx and INP & INN.

    Additional Questions: The port settings of the IC currently being tested are as follows. If there are any mistakes in the settings, please advise.

    • Since SPI communication is not used, the GDx terminal settings are based on datasheet 6.2.3.1 Table 6.
    • Is Hi input necessary for ASC_EN_PRI and ASC_EN_SEC even if they are not used?

    GDx Terminals:

    • GD0 = Hi (5V)
    • GD1 = Hi (5V)
    • GD2 = Lo (GND1)

    ASC Terminals:

    • ASC_EN_PRI = Lo (GND1)
    • ASC_EN_SEC = Lo (GND2)

    Reference: Other Terminal Settings

    • VCC1 = 5V
    • ASC_PRI = Lo (GND1)
    • INN = Lo (GND1)
    • INP = Hi (5V * PWM)
    • nCS = Lo (GND1)
    • SCLK = Not connected (Hi-Z)
    • SDI = Not connected (Hi-Z)
    • SDO = Not connected (Hi-Z)
    • VCECLP = -4V (VEE2)
    • CLAMP = -4V (VEE2)
    • VCP = +18V (VCC2)
    • VCC2 = +18V (VCC2)
    • DESAT = Lo (GND2)
    • AL1 = Lo (GND2)
    • ASC_SEC = Lo (GND2)
    • ASC_EN_SEC = Lo (GND2)
    • VEE2 = -4V

    OUTH1, OUTH2, OUTL1, OUTL2: Connected to 0.02uF assuming MOSFET gate capacitance.

  • 0 in reply to Toshihide Tanaka
    TI__Mastermind 25980 points

    Hi Tanaka-san,

    Could you check the status of the nFLTx pins? If there is no fault, then they should be high.

    Also, VCP should normally be above VCC2. What is the value of the decoupling cap between VCP and VCC2?

    Regards,

    Max Verboncoeur

  • 0 in reply to Max Verboncoeur
    Prodigy 10 points

    Hello Maxwell!

    The nFLT is 3.5V for both nFLT1 and nFLT2.
    *Both pins are measured at the voltage after passing through the RC filter (100Ω) with the pins unconnected.
    　The pull-up resistor inside the IC and the voltage divider of 100Ω are measured, can they be considered Hi state? (VCC1=5V)

    VCP and VCC2 are connected with only 0.1μF decoupling capacitor.
    *Datasheet P98 recommends a decoupling capacitor of 0.01uF to 0.1uF (0603 size, etc.).
    The capacitor used is CGA4J2X8R1H104K125AE, which has a capacitance of 0.1µF but a size of 2012

    Both VCC2 and VCP are +18.0V, and there is almost no potential difference between VCP and VCC2.

    I believe that the GDIC terminal input outputs are fine except for the OUTH output, but am I missing something?

  • 0 in reply to Toshihide Tanaka
    TI__Mastermind 25980 points

    Hi Tanaka-san,

    Would you be able to share a waveform of your PWM, the GDx pins, and the OUTx signal?

    Regards,

    Max Verboncoeur

  • 0 in reply to Max Verboncoeur
    Prodigy 10 points

    Hi Maxwell-san,
    sorry for the delay in getting back to you.

    I found the cause of the problem with the gate driver IC that I was discussing with you.

    The cause was found to be the pattern in which the gate driver IC is mounted.

    After correcting the pattern, the IC is working fine as shown in the attached figure.
    Red: PWM input (function generator output)Gate driver IC output
    Light blue: Gate driver IC output

    Now that we know that there is no problem with the gate driver IC and that it operates normally, please let me complete this question.