Hello Gamini,

This question has been assigned and will be reviewed and answered when possible.

Thank you,
Alan 

Hi Alan, 

We don’t think the issue is related to the cells or the battery construction for a few reasons.  First, they are high quality name brand cells, we are using a spot welder and using good industry standard processes with the tab construction and welding.  We don’t see the cell 1 voltage drop during normal charge discharge cycles (charging at 2.5 amp per cell, discharging at 6.5 amp).  The disparity seems to happen when the packs are sitting idle on the shelf.  If there were capacity issues between cells that should be apparent during normal charge discharge cycles, likewise if there is heating or bad connections between cells that should be exaggerated but more current and should be much more pronounced using the 6.5A discharge then the slow discharge from background bms parasitic draw.

 Since in our experience the cell voltage disparities happen during inactivity we have not been doing continuous logging as that would prevent the BMS from sleeping and would effect the parasitic draw of the BMS.

 We have instead just been taking snap shot log files on a regular basis for packs that are in storage or at events like after charging or discharging.

 Here is an example of one of our battery spreadsheets with cell data extracted from log files.  All discharges are at 500W with the BMS CUV threshold at 2.9V per cells and 2s delay, recovery is 3.0V, the digital load is set to cut off at 37V so when the BMS CUV hits the digital load shutdown but it’s the BMS doing the end of discharge no the digital load fundamentally.

 SN169 I believe is manifesting some capacity imbalance since with each discharge cycle the difference between cell 1 and the other cells keeps coming back, but that could easily be from extra stress imparted by the cell initially getting down to 1.8V.  The main concern is how it gets that far out of balance while sitting on the shelf in the first place.

For some reason it doesn't allow me to upload the file. SO copied the data instead. 

SN: 6

SN: 168

SN: 169

Hi Alan,

It just occurred to me that I cannot publish the log file here because of the NDA we have signed with the BMS vendor. Also , we don't have the log file created during the failure. The failure happens during storage over a few weeks and when it goes to shutdown. We have created a log file during discharging but I have to send you via email. Please let me know how to proceed.

Thanks

Gamini

Alan,

I am Gamini's coworker and would like to be added to the chat so I can give input as well without having to pass info through Gamini.

Thanks

Jason

Alan,

The main thing I wanted to add to the chat was that the battery from the log file we sent you went way out of balance when it was sitting on the shelf (cell 1 was 555mv lower)  Then we manually balanced the battery using an external charger (bypassing the bms) that brought the cell balance to 19mv spread at full charge and 38 mv spread at cut off.  We cycled that pack for 8 cycles now and each time the spread returns to about 19mv at top of charge and back up to 38mv at the bottom and there is no trend of this getting worse.  This is consistent with our in house testing and our customers, when the batteries are used regularly they appear to be maintaining cell to cell balance, but when they are put on the shelf with no cycling they become out of balance.

I also wanted to highlight the fact that we are seeing what we think is a high self discharge rate, I have two packs with nothing hooked up but a bms which should be in sleep mode and they are losing about 16.5mAh per day of capacity.  As Gamini had mentioned the bq78350R1 is on firmware V1.03 and V1.04 has fixes for improving the shutdown process and I am wondering if there is any chance that the chip is not properly entering low power state?

Finally I if I am understanding correctly V3.00 adds the ability for cell balance when the batteries are at rest not just during charge.  Its my understanding that typically balancing is only done during charging, but the fact that TI has added this capability seems to suggest otherwise.  Do you have any experience with balancing in the rest state and under what circumstances that is needed?

Thanks

Jason

Hi Alan,

We managed to update the V1.03 firmware to V3.0,0, hoping that we will have access to the new bits to enable Cell Balancing during Sleep. However, we only see CB_REST and not other bits such as NO_CMD, CB_NOSLEEP, CB_SLEEP. Also bit 1 CB_REST rather than CB_RLX and Bit0 CB instead of CB_CHG. Please see the uploaded file for bit mapping after the firmware update. Please let us know how to access the bit CB_SLEEP.

Thanks

Gamini