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UCD90160A: UCD90160ARGCT Watchdog Configuration

Sneha J S
Prodigy 40 points
Part Number: UCD90160A
Other Parts Discussed in Thread: UCD90SEQ64EVM-650, UCD90160

Tool/software:

Dear Team,

We are using the UCD90160ARGCT power sequencer in our design, and we are validating it with TI Evaluation Kit (UCD90SEQ64EVM-650).

Below attached is the Block diagram of the Watchdog circuit used in our design:



GPIO6 is configured as the watchdog input and GPIO12 as the watchdog output.
A periodic pulse is given from Zynq MPSoC to GPIO6 of UCD90160ARGCT (Watchdog Input).

Additionally attached the Screenshot of the configuration in GUI


We observed the following behaviour:
When the watchdog input (GPIO6) is pulsed periodically, the watchdog output (GPIO12) remains high, as expected.
When the input pulse stops, the watchdog output goes low — also as expected.

 However, our requirement is for the watchdog output to go low when the input pulse stops, and then automatically return to high. Currently, the output remains low and does not return high until we manually intervene.

 Could you please confirm:

  • Whether the UCD90160 supports this type of watchdog output reset behaviour?
  • If so, how can it be configured (via GUI or registers)?

We would appreciate your guidance on how to achieve the desired watchdog behaviour.



  • 0
    TI__Genius 9570 points

    Hi, unfortunately, UCD90160 does not support that behavior: if the counter is not periodically reset within the amount of time configured, the WDO pin is asserted and stays asserted until either the WDI pin is toggle, or SYSTEM_WATCHDOG_RESET command (D4h) is written to device.

    Regards

    Anne Ngo

    Texas Instruments

  • 0 in reply to Anne Ngo77
    Prodigy 40 points

    As per the datasheet (Figure 26: System Reset with Watchdog), we expect the SYSTEM RESET signal to be automatically released after the watchdog reset time or tracking delay.

    We implemented that in our design:

    • GPIO12 is earlier configured as the Watchdog Output (WDO) is now set as SYSTEM RESET in the GUI.
    • Watchdog Start and Reset Times are configured correctly.
    • Delay/Release timing is defined.

    Attached the image of Configuration in GUI for you reference:

    Observation:
    When WDI stops toggling, WDO(Configured as system Reset) goes low as expected. However, it does not return high automatically — it stays asserted indefinitely.
    We expected WDO to toggle (go low, then high) to allow CPU recovery, as described in the datasheet.

    Could you please confirm if there are any additional conditions/settings required ?

  • 0 in reply to Sneha J S
    TI__Genius 9570 points

    Hi, Can you send the project file (.xml) saved by Fusion GUI so we can have a look.

    Regards

    Anne Ngo

  • 0 in reply to Anne Ngo77
    Prodigy 40 points

    Hi,
    Please find the attached .xml file from fusion GUI, as requested.

    .UCD90160A_PowerSequencer.xml

  • 0 in reply to Sneha J S
    TI__Genius 9570 points

    Hi, Sneha,

    Change System Reset Delay Time to use "Delay Time" instead of "GPI Tracking Release Delay Time"; it should work.

    Regards

    Anne Ngo

  • 0 in reply to Anne Ngo77
    Prodigy 40 points

    Hi, Anne,

    We implemented the suggestions provided by you, and the watchdog functionality is now working. However, we observed an issue with the WDO pin behavior:

    • When the WDO is configured as active high, the output remains high from the beginning and goes low only when the WDI stops toggling.

    • When configured as active low, the output remains low from the beginning and goes high only when the WDI stops toggling.

    This behavior appears to be the opposite of what is expected. Is there anything else that we are missing out?

    Regards,

    Sneha

  • 0 in reply to Sneha J S
    TI__Genius 9570 points

    Hi, Sneha,

    When making changes, please make sure to store to flash, then power cycle device for Watchdog to work properly.

    Regards

    Anne Ngo