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BQ25620: About registor control

teritama
Expert 2165 points
Part Number: BQ25620

Tool/software:

Hi team,


Our customer is considering this device by USB BC1.2 supply on Type-C connector.

They have few question about this I2C control behavior.


1. Can this device control to fix SYS output from BAT path only or VBUS path only by registor change from CPU?
If it is possible, does Dynamic Power Management still have priority?

2. In this device SDP current limit is 500mA. If we need support USB100(current limit 100mA), is it possible by REG0x06_Input_Current_Limit Register setting?

3. Concern with question 2, recentry is it not require to support USB100? Is the trend only USB500 support in the case of USB BC 1.2 system in the world market?

Best regards,

teritama

  • 0
    TI__Mastermind 31420 points

    Hi Teritama, 

    Please see my comments below. 

    1) By register change CPU can force SYS output to be powered by BAT. This is achieved by setting EN_HIZ = 1. With this bit set buck converter is forced off. On the other hand there is not a way to force SYS output to be powered by only VBUS. If VBUS has sufficient power it will support SYS output, but there is no way via registers to disable dynamic power management where battery is allowed to discharge to support SYS in certain cases. 

    2) REG0x06 (IINDPM) setting can be configured to 100mA. Although please keep in mind that via BC1.2 detection SDP inputs will be set to 500mA input current limit. This host CPU will need to set REG0x06 to 100mA for this case. 

    3) The BC1.2 detection procedure developed for TI battery chargers does not support USB100. Input current limit will always be set to 500mA for an SDP adapter. 

    Best Regards,

    Garrett 

  • 0 in reply to Garrett Kreger
    Expert 2165 points

    Hi Garrett-san,

    Thank you for your comment.

    1) I understood that we can force SYS output to be powered from BAT anly and that there is no way to disable dynamic power management.
    In this connection, this device have the register about Q1 and Q4 (REG0x14_Charge_Control_0 Register, Q1_FULLON and Q4_FULLON ).
    In my understanding, this registor can force Q1 or Q4 open when these bit = '1b'.
    Is my understanding correct? I want to know the defference of operation between EN_Hiz and these register.

    2) If we need 100mA current limit, is it okey that set REG0x06 after SDP adapter detected? Before detected source type by D+/D-, Is Input current limit set as default?

    3) I understood that the BC1.2 detection procedure in TI battery charger category support only USB500 for an SDP adapter.

    Best regards,

    teritama

  • 0 in reply to teritama
    TI__Mastermind 31420 points

    Hi Teritama-san, 

    Please see my additional comments below. 

    1) The registers you refer to in REG0x14 do not allow you to force Q1 and Q4 on or off. If you refer to their register descriptions in table 8-18 in the datasheet you will see Q1_FULLON and Q4_FULLON bits allow you to force a certain RDSon of Q1 and Q4 (I.e. these registers relate to efficiency/ power loss through the IC). 

    These registers do not allow you to force off the FETs. EN_HIZ needs to be used if you wish to force off buck converter with VBUS input present. 

    2)Yes you can update REG0x06 to 100mA setting after SDP adapter has been detected. You are always free to set IINDPM via host MCU. IINDPM default is 3.2A, but please be aware any new adapter plug in will result in this register being updated based on input type detected. 

    Please let me know if you have any further questions. 

    Best Regards,

    Garrett 

  • 0 in reply to Garrett Kreger
    Expert 2165 points

    Hi Garrett-san,

    Thank you for additional explanation. I understood both of answer.

    I have additional question about registor.

    In this device, I understand that when VVBUS < VVBUS_UVLO, BATFET_CTRL_WVBUS = 0 and QON become Low over tQON_RST, this devise initiates a full system power reset.

    Can we privent this reset occure by REG0x18 BATFET_CTRL control?

    Best regards,

    teritama

  • +1 in reply to teritama
    TI__Mastermind 31420 points

    Hi Teritama-san, 

    teritama said:
    In this device, I understand that when VVBUS < VVBUS_UVLO, BATFET_CTRL_WVBUS = 0 and QON become Low over tQON_RST, this devise initiates a full system power reset.

    For the condition you outline there is unfortunately no way to prevent system power reset via register setting. Design will need to ensure via hardware that QON pin is not pulled low for approx. 12.5 sec when VBUS < Vvbus_uvlo. 

    I will also note if your customer has no intention of using QON this pin can be left floating and in that case system power reset is always prevented. 

    Best Regards,

    Garrett 

  • 0 in reply to Garrett Kreger
    Expert 2165 points

    Hi Garrett-san,

    Thank you for your kindly supports. It make sence.

    The Customer is positively considering to use this device.

    Best regards,

    teritama