TLV767-Q1: Would like to enhance thermal dissipation performance by optimizing PCB layout design

Hi Yamamoto-san,

Here's an app note that discusses the impact on board layout for thermal performance: 

An empirical analysis of the impact of board layout on LDO thermal performance: https://www.ti.com/lit/an/slvae85/slvae85.pdf

In general, having more ground copper that connects to the thermal pad (on internal or external layers) helps to spread heat, and in particular, the top and bottom layers are most effective at removing heat since heat can leave these layers to the ambient air. This app note shows that the RθJA can be reduced by as much as 50% with good layout but note that in most applications there is not enough board space to have enough copper to achieve this. In this customer's application, with 1.56W dissipated in the pass FET, and if the board layout resembled the JEDEC High-k board layout, the max junction temperature would be 85C + 1.56W * 51.9C/W = 166C. So, to keep the junction temperature under 150C, they will need to improve the RθJA by at least 20% relative to the High-k board layout. This is possible, but only if they have enough board space and internal ground layers to spread the heat. 

Regards,

Nick

Hi Nick,

Thank you so much for sending me the material. It is what I wanted! 

Nick Butts said:

This is possible, but only if they have enough board space and internal ground layers to spread the heat. 

I agree with you. My customer needs to consider the placements of other components.

I have a question regarding Tj and Tsd(shutdown). In my understanding, if the temperature exceeds Tj, the IC gets broken, and the IC cannot properly work. But Tsd(shutdown) is higher than Tj. Is this device possible to exceed Tj since Tsd exceeds Tj? How should I understand Tsd(shutdown)?

Best regards,

Shunsuke Yamamoto