Tool/software:
Hi,
We are currently using the TPS3808G33 supervisor IC in our design to monitor the system supply voltage. As per the datasheet, the expected behavior of the IC is as follows:
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RESET assertion should occur immediately (no delay) when the voltage on the VSENSE pin drops below the threshold voltage VIT−.
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RESET deassertion should occur after a programmable delay (td), determined by the capacitor connected between the CT pin and GND, once the voltage on the VSENSE pin rises above the threshold voltage VIT+.
However, we are observing unexpected behavior:
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When the voltage on the VSENSE pin drops below VIT−, the RESET output is not asserted immediately. Instead, there is a delay of approximately 0.8 seconds before RESET is asserted.
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When the voltage on the VSENSE pin rises above VIT+, the RESET deasserts after a delay of around 1.5 seconds, which aligns with expectations based on our CT value.
Additional context:
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We are using a 0.22 µF capacitor connected between the CT pin and GND.
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The behavior observed is consistent and repeatable under controlled test conditions.
This indicates that the IC is applying the delay timer on both RESET assertion and deassertion, which deviates from the datasheet specification that RESET should be asserted immediately when VSENSE goes below the threshold.
We would appreciate clarification on this behavior:
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Is there any internal debounce or filtering mechanism that could introduce this delay during RESET assertion?
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Could the large CT capacitor be influencing assertion behavior unexpectedly?
