TPSM5D1806: TPSM5D1806 Dual rail output configuration - No voltage output

Mohan,

I am forwarding this post to find a local FAE. 

In the meantime, if you have scope plots (with traces En1, EN2, SW1, VOUT1 ) or pcb images, please share. 

For the 3.3V rail output, the R110 should be 56kohm with R112 of 10kohm.   

But R110 and R112 are 100k and 10k respectively on the schematic which would give 5.5V. 

David 

David,

Thanks for response, We have not yet made the scope plots of the traces that you have indicated.  I will share the PCB images going forward.

R110 we have corrected it already on the board but yet to update the schematic.

"But R110 and R112 are 100k and 10k respectively on the schematic which would give 5.5V. "

We have already implemented this change on the board to correspond to design for 3.3V.

Thanks

Mohan  

Please post pcb layout images and scope traces when you have them

Hi David,

Please find the PCB snap shot docs attached.

We are able to see the BP5 pin @ 5V.

We also de populated the PGood 1 and 2 pull ups  that was originally in design.  

The outputs are 0.5V and not 1.8V and 3,3V, 

What is the scope traces you need? Will try to provide accordingly.

Thanks

Mohan 

TPSM5D1806RDB PCB snapshots.pdf

A 0.5V output implies the R112 and R99  resistors (low side feedback) are not completely connected.    

Typically, I would request scope plots of the sw node.   But on this device, the sw node does not need an external

connection to a component and not easily probed.   

I need to verify the switching frequency when the device is regulating after power up.  

Can you use 1us/div and ac coupled <=20mV/div  and probe vout1 pin 26 to GND pin 27 or probe vout2  to gnd pin.   

Trigger on the ripple so the switching frequency can be estimated.   From 12V to 0.5V at 2MHz switching, 

I think there will be pulse skipping because of the minimum on time. 

Capture on Scope

During power up use 1ms/div and normal trigger on vin or enable and capture Vout, EN, VIN, BP5

l will work on this and provide an update in 2 days from now.

Thanks

Mohan 

thank you

David,

Probed for the connection for the resistors R112 and R99, these respectively seems to be connected to ground on one end and the other end to their respective counterpart resistors of the feedback network.

This was checked on tow separate boards, both were fine.

On board one :3V3 output is at 0.48V and the 1V8 rail is at about 0.60V

On board one :3V3 output is at 0.4V and the 1V8 rail is at about 0.50V

on Both the boards BP5 output is at 5.0V

working on the oscilloscope traces, Will update you on this shortly.

One more aspect that I found on the datasheet is that for a Vin of 12V, Per table 7-1 none of the voltage rails that we require are listed out (that is 1.8V and 3.3V). can you confirm this.

The Webbench simulation  schematic is as below and we have mod the design on the board to reflect this.

Thanks

Mohan 

Meant to say

On board one :3V3 output is at 0.48V and the 1V8 rail is at about 0.60V

On board two:3V3 output is at 0.4V and the 1V8 rail is at about 0.50V

Based on the table and the switching frequency setting of 2MHz (53.6kohm) and input voltage of 12V. 

The device should support between 1.4V to 3.2V upto 6A load and between 1.4V to 5.5V upto 5A load. 

Thank you, The oscilloscope plots will help give some insight on the issue. 

Hi, 

We are working on this, Have you folks reviewed the PCB layout files that I sent earlier.

We used the eval board of this DC-DC module and configured the board to match the schematic design that Tsecond has on its board. 

We are able to see that Eval board U1(Dual output type) is able to generate the 3.3V and the 1.8V.

Will share the traces shortly.

BR

Mohan 

i'am Trying to upload to some initial oscilloscope plots, the TI support portal is not letting me do so.

Can you help me on this.

Mohan 

The First Image:- Tsecond Board. O/P node trace

Second Image:- TI Eval Board O/P node trace

Third Picture: - The trigger option available on my oscilloscope does not have the trigger to ripple option, Can you advice on this.

Thanks

Mohan  

Was able to extract a more clearer plot / trace of the two output nodes ,

There seems to be some switching happening at the output but not very prominent in terms of voltage swing

Thanks for the waveforms,  the device is switching but differently.  

What is the load current for the tsecond board. 

I reviewed the pcb layout, it is pixelated and difficult to review connections.  

My observations It looks like the BP5 and VIN1 capacitors are on bottom side of board and VIN1 and VIN2 input capacitors do not have symmetrical placement.  But I would like a better image to review the feedback resistors connections to the vout's and ground. 

Use the edge trigger, positive.

Lets focus on one channel, use dc coupling on probe check En1, Vout1 (AC) , VOUT1 (DC), VIN1 pins(33 to 35) to PGND (pins 24-26). 

probe near vout feedback connections and document where probes were placed during measurements. 

Capture start up of Vout1 using single shot trigger on Vout1 DC or normal mode DC coupling when powering up. 

Then capture Vout1 after operating in steady state. 

Capture VIN1 pins(33 to 35)

Capture VIN2 pins(4 to 6) 

Capture BP5 

Thanks,

Will work on a better PCB data for you and forward it shortly.

Can higher ESR caps on output have a negative impact on the output switching and loop stability.

The output caps that are in Tsecond design seem to have a higher ESR than the ones on the eval board.

Will work on the other plots and forward it to you.

BR

Mohan 

The load current is 1A for 1.8V rail and 1A for 3.3V rail.

Yes, higher esr capacitors can affect loop stability, but it will depend how much greater.   

Placing tsecond board capacitors on evm would be an interesting experiment. 

The schematic is showing 22uF ceramics which I assume is ~5mOhm.

Ceramic capacitors have a dc derating that must be factored into the analysis. 

 A 100uF 6.3V is not 100uF at 3.3V, it will be ~50uF.   Not having enough Cout can cause instability

PCB layout issues and noise issues can present as an instability. 

Yeah, Placing the Tsecond Caps on the Eval board would be a good thing to do

if you would like me to review capacitors, share the part numbers for the capacitors or specs 

Here are the capacitor details

22uF

Capacitors with ref des below, have this capacitor part( this is for the I/P and O/P capacitors)
C224,C225,C226,C227,C228,C229,C230,C231,C232,C233,C234,C235,C236,C237,C238,C239,C240,C241

GRM188C61E226ME01J

www.mouser.com/.../GRM188C61E226ME01J

2.2uF

Capacitor with ref des C146 have this capacitor part.
C0603X7R6R3-225KNP

www.digikey.com/.../12332824

Do these PGND pads on the bottom side of the converter module require a corresponding exposed pad on the PCB?

The section marked in yellow, 

I have checked the eval board, that seems to not have it.

Mohan

The PGND 47 to 51 are electrically connected to PGND pins 10-12/27-29.   

It is best to connect to ground plane underneath to help dissipate power, especially for a 2MHz solution. 

The PGND pins 27-29 are only connected to the ground plane under device and couple of vias near the pins. 

The current on channel 1 has a longer path to cout ground. 

Your output capacitors seem okay.   I can't find the part number in sim surfing on murata, but the ceramic capacitors have low esr.   

If cap was alum electrolytic with high esr, it could affect stability.    The caps are 25V so the derating should be less significant, than a 6.3V. 

I suspect there is an issue with pcb layout, compare the layout with   https://www.ti.com/lit/ug/sluuc66b/sluuc66b.pdf on page 4-7. 

The input voltage capacitor are on top and bottom. I would try making the layout more symmetrical

Use large contiguous copper areas on same layer as device VIN, VOUT, and PGND power planes to reduce conduction loss

Place ceramic input and output capacitors very close to the device to minimize the parasitics.  

I find figure 1 helpful in the doc Common Mistakes in Power-Supply Layouts and How to Avoid Them

Mohan

Attached are some mods to consider.    If the solder mask can be scratched and copper exposed. 

A capacitor could be connected closer to vin to pgnd on top level (see the green markup).   

 Also, on bottom the caps rotated and it will shorten the ground path to pgnd pin.

In previous post, I downloaded and removed the detailed pcb images, since confidential was written on them. 

pcb_mods.pdf

David,

Noted, 

We will do the mod you suggested and get back to you on this shortly.

the other update is that we mounted the Tsecond board O/P caps on the TI eval board, the EVAL was able to  still output the 1.8V.

Thanks

Mohan 

We have modified the circuit on the dual output section of the eval board to match the design in Tsecond board(interms of the components type and value). Even with this mod the eval board is functional in outputting the 3.3V and the 1.8V).

The only difference currently between the mod eval and the Tsecond board is with respect to the SS (Pin 39), in the EVAL board this pin is pulled down to ground and the tsecond board has this pin floating(NC per datasheet).  Can you clarify if this difference is of any impact.

Mohan 

Mohan,

SS pin will not impact the dual output configuration.

When mode is selected for dual output, the input to SS pin is ignored internally.   

In dual config, the soft start times are generated by an internal refdac circuit. 

Thanks Noted

Thanks for the reply.

no need to reply further.  I’m here when there’s new information or questions,

David,

We have been able to get the converter module working, the reason for the earlier issues - were wrong components being populated during assembly, especially the Mode resistor and feedback networks.

Thanks for your support on this so far.

BR

Mohan