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TPS3899: TPS3899DL31DSERQ1 : Failure Analysis Request

Pradeep Prabhu G
Prodigy 10 points
Part Number: TPS3899

Tool/software:

Hello Team,

Need quick response for below topic,

I couldn't get a clear answer to the following statements from your feedback,

“In this situation, the SENSE voltage is applied to the IC before reaching the VDD POR threshold of 700mV, which is the specified minimum for proper operation. While I agree that this may fall within an "Undefined" region of the IC's operation, it's important to note that the datasheet does not specify that this behavior is "Forbidden." Therefore, this is not the cause of the abnormal behavior.

According to the datasheet timing diagram below and the configuration used in our application (CTR Open or NC), the IC's reset should go high within 380µs (Max Delay), based on the datasheet values (tSTART = 300µs max + tD = 80µs max) even SENSE signal applied before VDD supply.

Thank you

RE_ Failure Analysis Request.msg

  • 0
    TI__Genius 9700 points

    Hi Pradeep, 

    Thanks for reaching out. I'm happy to help with your inquiry. 

    VPOR is basically the minimum required VDD voltage that RESET can react depending on VDD and SENSE pin voltage. Depending on Active high or Active low device, the device will held accordingly. 

    It seems like you are asking for active low device behavior. And if there is no CTR capacitor, as you highlighted it should be pull itself high( if  SENSE> Vit & VDD> VDD(min)). Your understanding is correct.

    Hope this clarify, 

    Best,

    Sila 

  • 0 in reply to Sila Atalar
    Prodigy 10 points

    Could you please clarify SENSE signal applied before VDD supply is not an issue(Waveform attached below) according to the datasheet Figure 6-1?

    In our design, the SENSE voltage is applied to the IC before reaching the VDD POR threshold of 700mV, which is the specified minimum for proper operation. While I agree that this may fall within an "Undefined" region of the IC's operation, it's important to note that the datasheet does not specify that this behavior is "Forbidden." Figure 6-1 in datasheet.

    According to the datasheet timing diagram Figure 6-1 in datasheet. and the configuration used in our application (CTR Open or NC), the IC's reset should go high within 380µs (Max Delay), based on the datasheet values (tSTART = 300µs max + tD = 80µs max) even SENSE signal applied before VDD supply.

    Please clarify?

  • 0 in reply to Pradeep Prabhu G
    TI__Genius 9700 points

    Hi Pradeep, 

    Sense voltage can be applied before VDD. 

    I learned from my team that TI run an FA analysis on this unit already, and according to bench and ATE result, it seems like the unit is good. I'm not sure what is causing this behavior, but your understanding is correct. 

    If you'd like to remove the IC from your board and test it, I would recommend using our Evaluation module for further analysis.  

    TPS3899EVM — The TPS3899 evaluation module (EVM) is a platform for evaluating the TPS3899 product, which is a 6-pin voltage supervisor and reset IC

    One thing you can do is letting the device run (VDD> VDD_min & Vsense>Vit-) even if the RESET is not pulling itself. To make sure there is no big delay.

    Do you have only one unit behaving like this?