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UCC29002: Verifying stability of the load sharing circuit

B C
Prodigy 30 points
Part Number: UCC29002

Tool/software:

Hello,

I'm using the UCC29002-1 controller in a low side current sense, high voltage configuration to load share between 4 power supplies with a varying load between 0-30A.  I have built a single board with this circuit and from my basic testing with resistive loads and the real target load,  current appears to be shared evenly across the 4 power supplies.   Is there any specific testing or analysis that you would recommend doing to verify stability of the load sharing circuit prior to doing a larger manufacturing run?

I can send the schematic over private message if needed.

Thanks,

BC

  • 0
    TI__Mastermind 40580 points

    Hello BC, 

    I don't think that a schematic diagram is necessary at this point. 

    I'm glad that your prototype board is working to your satisfaction.

    If designed properly, the current-sharing loop response will be much slower than the power module voltage-loop response. 
    It is designed this way so that the current loop does not fight the V-loop for control during transient conditions. 

    To verify loop stability, the V-loop transient response of your combined 4-supply voltage source should be basically the same as for a single module when subjected to load and line disturbances (steps, ramps, etc.) (magnitudes proportionally scaled to the number of paralleled modules).  
    Current-sharing can be considered to be a steady-state condition, so currents from different modules may vary considerably during the transient response time. Some modules may hit their current limit during significant load steps, but accurate current-sharing should settle and resume after ~10 times the duration of the voltage transient.

    I suggest to start with sharing 2 modules in parallel and apply small step loads and unloads and monitor the current sharing and combined output voltage for signs of instability.  When satisfied with the results, increase the step sizes gradually and reassess each time.  
    Do similar tests with line steps in gradually increasing severity. 

    When 2 modules pass all of your tests, repeat them all with 3 modules in parallel.  
    When 3 modules pass all of your tests, repeat them all with 4 modules in parallel.  

    You can consider whether to build up another board or two for more assurance of repeatable performance. 

    Regards,
    Ulrich