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TPS25948: TPS259480AYWP - the SPLYGD (non-inverted) Vol level

Part Number: TPS25948

Hi,

Could you please help clarify the SPLYGD (non-inverted) pin Vol level when not active in TPS259480AYWP.

This is an OD signal that is asserted high when the input supply is valid and the channel has completed the inrush sequence.

What should be Vol_max in the following cases? 

How can I estimate the Strong or Weak PU values for Vol?

Is the Iq current +-3uA related to the active high state?

SPLYGD Vol=? VIN = 0V, Strong pull-up

SPLYGD Vol=? VIN >3.3V, Strong pull-up

SPLYGD Vol=? VIN >3.3V, Weak pull-up

SPLYGD Vol=? VIN <3.3V, Strong pull-up

SPLYGD Vol=? VIN <3.3V, Weak pull-up

I am sharing with you the implementation based on the SPLYGD signal and N-channel MOSFET with High Vgs_th.

USB_2.0_EN mechanism.ppt

Regards

Vitaliy

  • Hi,

    Could you please advise?

    Vitaliy

  • Hi,

    Could you please advise?

    Vitaliy

  • Hi Vitaliy,

    Let me explain the internal mechanism little bit and then answer your question. In this device, when the Vin is high enough for device to power its internal rail, SPLYGD is controlled by the device and do not depend on pull ups.

    SPLYGD Vol=? VIN >3.3V, Strong pull-up

    SPLYGD Vol=? VIN >3.3V, Weak pull-up

    So in this case SPLYGD will depend on OUT voltage. If the OUT is high, SPLYGD will be high else it will low.

    In case of Vin is low, device pull down FET will take power from pull up itself so that SPLYGD can still remain low. Here the voltage appearing at the SPLYGD pin will depend on the pull up strength. 

    this table from datasheet helps in answering your question. 

    So for the your implementation of NFET controlled with this signal should work fine as even when some voltage buildup is happening, the FET won't falsely turn on due to high VTH of 1.3V.

    How can I estimate the Strong or Weak PU values for Vol?

    I checked this. When we mentioned weak pu, it is around 20uA pull up and when we mentioned strong pull up, it is around 240uA. You have 3.3V pullup so resistor value can be calculated accordingly.

    Is the Iq current +-3uA related to the active high state?

    This is leakage that can happen from pullup through this pin to GND. This will happen when FET is off i.e. SPLYGD is high in this case.

    I apologies for the delayed response. I was stuck in some testing and wasn't able to respond earlier.

    Best Regards,
    Arush

  • Hi Arush,

    Thanks for your clarification. It is a good idea to add this Vol I sink Strong/Weak PU information to the spec.

    Therefore, if I would like to keep SPLYGD Low before the Vin attachment, I have two options:

    Weak PU: To keep SPLYGD Vol <0.99V

    (3.3V - 0.99V) / 0.00002A < 115,500 Ohm

    Strong PU: To keep SPLYGD Vol <0.6V

    (3.3V - 0.6V) / 0.00024A > 11250 Ohm

    In my case, when n-channel Vth is greater than 1.3V, both options are valid.

    From the current drain perspectives, to reduce the current drain, I can use a high PU 100k value to reduce the current from the battery when Vin is not connected (most of the time).

    Are there any other concerns I need to address?

    Regards

    Vitaliy

    100

  • HI Vitaliy,

    Thanks for your clarification. It is a good idea to add this Vol I sink Strong/Weak PU information to the spec.

    Usually this information is not needed to most of the customers and may result in unnecessary confusion but I understand your point. 

    In my case, when n-channel Vth is greater than 1.3V, both options are valid.

    Yes.

    From the current drain perspectives, to reduce the current drain, I can use a high PU 100k value to reduce the current from the battery when Vin is not connected (most of the time).

    Are there any other concerns I need to address?

    Yes, this sounds good. I don't see any concerns.

    Best Regards,
    Arush