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TPS6594-Q1: Configuration related Query

Manish Kolte
Prodigy 60 points
Part Number: TPS6594-Q1

Tool/software:

Hello, 

1. I am using TPS6594 PMIC and below are configuration set 

  • BUCKn_GRP_SEL = 1 (MCU rail Group)
  • MCU_RAIL_TRIG = 0 (Immediate shutdown)

In this case my understanding is, in case of BUCK regulator overvoltage PMIC will trigger IMMEDIATE_SHUTDOWN and nRSTOUT and nRSTOUT_SOC both will be triggered. 

Is my understanding correct?

2. Is nRSTOUT will be trigged in all below error conditions ?

Power Rail Output Error
Boot BIST Error
Runtime BIST Error
Catastrophic Error
Watchdog Error
Error Signal Monitor (ESM) Error

3. For each PMIC fault Corresponding error interrupt (for Ex: BUCKn_ILIM_INT, BUCKn_OV_INT etc) is for notification and logging .. is it correct?

  • 0
    TI__Guru* 77811 points

    Hi Manish,

    To help give you the most detailed answer, can you please share the full OPN (orderable part number) of the device you are using? This helps us to know what NVM configuration is in the device. 

    Regards,

    Katie

  • 0 in reply to Katie Pier
    Prodigy 60 points

    Hi 

    Full part number - TPS6594133ARWERQ1

  • 0 in reply to Manish Kolte
    TI__Prodigy 40 points

    Hello Manish,

    For your first question, that configuration should result in exactly what you've described: Immediate shutdown followed by a reset of the MCU through nRSTOUT and the SoC through nRSTOUT_SoC. I will note that this is not the default configuration for the TPS6594133ARWERQ1, but should work as long as you set the right registers.


    In regards to your second question, most of those will result in a falling edge of nRSTOUT as you have described:

    Power Rail Output Error
    Runtime BIST Error/Failure
    Catastrophic Error
    Watchdog Error (through warm reset)
    Error Signal Monitor (ESM) Error (Sometimes warm reset, sometimes just nRSTOUT)

    However, the Boot BIST Error/Failure does not send a falling edge on nRSTOUT, as nRSTOUT will not have been high when this issue would occur.


    I am still looking into your third question, but in general, you are correct that the interrupts are meant for notification and logging of issues. Although the Watchdog may also make use of these interrupts to identify when it needs to restart the device if one occurs and the Watchdog is enabled (depending on your configuration). Either way, the interrupt register values should remain after the fault. I will verify this and look for any exceptions and let you know.

    Regards,

    Ethan

  • 0 in reply to Ethan Pena Perez
    Prodigy 60 points

    Thanks a lot for immediate and clear reply. Could you please confirm on question 3 as early as possible?

  • 0 in reply to Manish Kolte
    TI__Prodigy 40 points

    Hi Manish,

    I have found these exceptions in the following User's Guide: https://www.ti.com/lit/ug/slvuci2a/slvuci2a.pdf?ts=1750709064295 

    Figure: Section 5.2 PFSM Triggers, with Table 5-1 showing GPIO10 going Low as a trigger to commence safe orderly shutdown

    Figure: Table 5-1, showing GPIO8 Low as a non-immediate, PWR_SOC_ERR trigger

    As visible in the partial tables above (found in Section 5.2), GPIO pins 8 and 10 are used as state transition triggers in the TPS5294133A's configuration, meaning that they will not indicate their interrupts as typical GPIO pins would. These were the interrupt exceptions I was referring to in my last response, as they would mark interrupts for the errors they are representing rather than the general-purpose rising or falling edge of that GPIO pin that you may typically expect. I was fairly certain these were exceptions, but I needed the extra time to validate my understanding, and I appreciate your patience.

    The other GPIO pins and interrupts should behave as you understand them to and as I described in my previous response.

    Regards,

    Ethan