UCC28064A: Select the constant Rz and sudden load change

Hello Takahara-san,

The primary purpose of Rz in the compensation network on the COMP pin is to provide some phase-margin boost around the loop-gain 0dB cross-over frequency for improved stability.  Loop stability is a small-signal issue and the compensation component values are calculated under small-signal perturbation conditions. 

A 100% load-step is a large-signal condition, but the small-signal values still affect the loop response.  
The voltage on COMP (Vcomp) determines the overall output power level being delivered by controlling the allowable MOSFET on-time.  Low Vcomp = shorter on-time = low Pout; high Vcomp = longer on-time = high Pout.  
During steady-state load conditions, Vcomp is a nearly-constant voltage with a very small ripple superimposed on it.  The transconductance error-amplifier output current (at COMP pin) is nearly zero. 

During a drastic load-step, the output voltage drops significantly and the error between VSENSE and the internal VREF increases, which also increases the COMP current into Rz, Cz, and Cp.   Cz is a high value, so its voltage does not change much over an AC half-cycle.   Cp is a low value so its voltage can increase from the higher COMP current flowing into it. As Vcomp rises, a voltage difference develops across Rz from the fast rising Vcp minus the slow rising Vcz.  

If Rz is a low value, the low voltage across Rz diverts most of the COMP current into Cz and further rise in Vcomp is limited by rise in Vcz.  Since this rise is slow, the V-loop is slow to provide higher output power to restore Vout regulation after the step-load, and Vout can droop significantly while Vcomp is rising. 

If Rz is a high value, the voltage across Rz can rise higher quickly before most of the COMP current is diverted into Cz.  Since this rise of Vcomp is fast, the V-loop is faster to provide higher output power to restore Vout regulation, and Vout does not droop as much. 

Your Condition B indicates that Rz was increased 10X over Condition A, but also Cz was reduced by 10X at the same time.  Is this correct? 
That means that you have increased the V-loop bandwidth by ~10X, because Cz determines where the loop cross-over frequency occurs.  Higher cross-over frequency will introduce considerable distortion into the input current.  

The UCC28064A Excel calculator tool can be used to establish the nominal values for the compensation components. https://www.ti.com/tool/download/SLUC645 
I suggest to keep the values recommended for Cp and Cz.  Start with the calculated Rz value and evaluate system performance.  Rz can be increased to improve transient response, but make incremental changes and re-evaluate.  Rz too high will also increase current distortion.   
There are no practical upper or lower limits for Rz.  The optimal value is relative to the system loop characteristics and to the Cp and Cz values.
Higher and lower Rz will simply be more and more non-optimal.  
Impractical limits are Rz = 0 ohms where Cp and Cz simply form one big capacitor with negligible phase margin, and Rz > 500kR where <10uA current will force Vcomp to the ~5V clamp level (always driving max power).   

Regards,
Ulrich

Hello Takahara-san,

I think higher THDi is the main disadvantage of low Cz and high Rz.  
Frankly, I'm surprised that it is only 3.4%.  

Maybe this measurement corresponds to low input voltage.  Make sure to check THDi at your maximum input voltage to verify acceptability. 
I also suggest to verify that your PFC voltage-loop stability maintains sufficient phase margin at high line. 

Regards,
Ulrich