Other Parts Discussed in Thread: LP87745, LP87744-Q1, , LP87743-Q1
Tool/software:
We are using the LP87745 PMIC in our design and require clarification on the precise watchdog reset timing under specific failure conditions in Question & Answer (Q&A) mode.
We have performed some tests and would like to confirm if our observed behavior is expected.
Our Configuration:
Watchdog Mode: Question & Answer (Q&A)
PMIC_WD_WIN1_CFG: 70 ms
PMIC_WD_WIN2_CFG: 70 ms
PMIC_WD_THR_CFG: 0x00 (Configured for reset on the first failure)
Our Software Servicing Sequence:
Our software services the watchdog at the following points in the 140ms Q&A cycle:
Answer 3: Sent at 10 ms (within Window 1)
Answer 2: Sent at 20 ms (within Window 1)
Answer 1: Sent at 30 ms (within Window 1)
Answer 0: Sent at 100 ms (30 ms into Window 2)
Observed Behavior and Questions:
We have tested two main failure scenarios and need to confirm the reset mechanism.
1. Window Timeout (No Answers Sent)
Observation: If our software sends no answers, a system reset occurs after the full 140 ms cycle (Window 1 + Window 2) has expired.
Question: Can you confirm that this is the correct behavior for a timeout failure?
2. Incorrect Answer in Window 1
Observation: When we intentionally send an incorrect answer during Window 1, we observe a consistent pattern:
If we send an incorrect Answer 3 (at 10 ms), the reset occurs ~90 ms later (after sending Answer 0 at the 100 ms mark of the cycle).
If we send an incorrect Answer 2 (at 20 ms), the reset occurs ~80 ms later (after sending Answer 0 at the 100 ms mark of the cycle).
If we send an incorrect Answer 1 (at 30 ms), the reset occurs ~70 ms later (after sending Answer 0 at the 100 ms mark of the cycle).
Question:
Our results suggest that even with the failure threshold set to 0x00, the reset is not triggered immediately upon detection of the incorrect answer.
Instead, the PMIC appears to latch the error and trigger the reset at a deterministic point later in the cycle (~after sending Answer 0 at the 100 ms mark of the cycle).
Can you please confirm if this is the expected behavior?
