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BQ76922: Standalone schematic review

Muki
Prodigy 220 points
Part Number: BQ76922
Other Parts Discussed in Thread: TIDA-010208, , EV2400,

Tool/software:

Hi Guys,

I'm attaching a schematic for a standalone design - 4S Schematic

The schematic is based on BQ76922EVM and TIDA-010208. Kindly go through and suggest if any changes are recommended

1. I've disabled the internal LDO by connecting REG1 to VSS. Should I enable it and provide 3.3V pull-up for the I2C lines ? (I'm hoping that the EV2400 will provide the pull-up, for OTP)

2. I've used 10M resistors for PCHG and PDSG gate (R9, R10) - Is 1M recommended ?

Thanks & Regards,

Muki

  • 0
    Prodigy 220 points

    Hi guys,

    Is someone assigned to review my schematic ?

    Thanks & Regards,

    Muki

  • +1
    TI__Prodigy 740 points

    First, I'll answer your specific questions:

    1. If using the EV2400, then the user guide does say the SCL/SDA pins are pulled up to 3.3V with a 20kΩ Resistor. Just be aware if the BQ76922 is powered up before the EV2400, then the I2C pin of the BQ76922 will appear to be floating until the EV2400 is powered-up.

    2. The PCHG and PDSG drivers are limited in the current they can sink while enabled. As such, it is recommended to use 1MΩ or larger resistance across the FET gate-source. So 10MΩ should be fine, it will turn on slower than the recommended 1MΩ.

    Some further schematic review notes below:
    - The     CHG series gate resistance is somewhat small compared to the BQ76922EVM and TIDA-010208. Your application may need this if it demands faster CHG FET turn-off/turn-on speeds. But this may come at the cost of a higher inductive spike.
    - The PCHG/PDSG drain resistor is much smaller than the BQ76922EVM and TIDA-010208, which use 1kΩ and 255Ω respectively. You application may demand a much lower drain resistance for the PCHG/PDSG FETs but I just want to point this out.

  • 0 in reply to Gavin Long
    Prodigy 220 points

    Hi Gavin,

    Thank you for the quick response

    1. Understood. I choose to leave the internal LDO disabled

    2. Got it. Will test with both 1MΩ and 10MΩ

     

    Based on your notes :

    a. I've used this specific FET and gate resistance in previous designs. Works well for me. Will test again for spikes with an oscilloscope

    b. This is intentional. I've made the calculations with reference from previous E2E posts and the particular voltage levels of my design. If the test fails, will switch to the resistance values from the reference designs

    Note : It seems I've forgotten the 470pF capacitors recommended in parallel with the 5 thermistors. I'll go ahead and add that

    once again, thank you for the quick response

    Regards,

    Muki