Tool/software:
We would like to share an observation related to the PMIC behavior during a long startup issue in the SBL (Secondary Boot Loader) phase.
During SBL startup, we read specific PMIC registers to retrieve error information from the previous software run within the same power cycle. We have noticed that in cases where a long startup occurs, the PMIC appears to trigger an ORD_SHUTDOWN_INT reset due to a CONFIG_CRC_INT error during the previous SBL startup.
Below is a comparison of PMIC register values observed in working and non-working scenarios:
|
Register |
Working Scenario Value |
Non-Working Scenario Value |
Interpretation |
|
INT_TOP |
152 |
168 |
Indicates pending interrupts in MODERATE_ERR_INT and MISC_INT registers |
|
INT_MISC |
1 |
0 |
Suggests LBIST was not completed |
|
INT_MODERATE_ERR |
0 |
8 |
CRC error detected during register checking |
|
INT_FSM_ERR |
80 |
82 |
Indicates an orderly shutdown was detected |
Based on the values of INT_MODERATE_ERR and INT_FSM_ERR, it appears that a reset is triggered during the SBL startup, causing the startup sequence to restart from the beginning. This behavior contributes to the increased wake-up time.
We would like to understand the possible causes of the CRC error that leads to the ORD_SHUTDOWN_INT reset.
This issue appears to be very rare — occurring approximately once in every 3000 iterations.
